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MC68HC05BD3D/H
MC68HC05BD3 TECHNICAL DATA
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TECHNICAL DATA
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GENERAL DESCRIPTION PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GENERAL DESCRIPTION PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3 MC68HC05BD5
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MC68HC05BD3 MC68HC705BD3 MC68HC05BD5
High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and !are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
(c) MOTOROLA LTD., 1996
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Conventions
Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Unless otherwise stated, blank cells in a register diagram indicate that the bit is either unused or reserved; shaded cells indicate that the bit is not described in the following paragraphs; `u' is used to indicate an undefined state (on reset).
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TABLE OF CONTENTS
Paragraph Number TITLE Page Number
1 GENERAL DESCRIPTION
1.1 Features.................................................................................................................1-1
2 PIN DESCRIPTION AND I/O PORTS
2.1 PIN DESCRIPTIONS.............................................................................................2-1 2.2 Pin Assignments ....................................................................................................2-2 2.3 INPUT/OUTPUT PORTS.......................................................................................2-3 2.3.1 Port A ...............................................................................................................2-3 2.3.2 Port B ...............................................................................................................2-3 2.3.3 Port C ...............................................................................................................2-4 2.3.4 Port D ...............................................................................................................2-4 2.3.5 Input/Output Programming...............................................................................2-4 2.3.6 Port C and D Configuration Registers..............................................................2-5
3 MEMORY AND REGISTERS
3.1 3.2 3.3 3.4 3.5 3.6 3.7 Registers ...............................................................................................................3-1 RAM (MC68HC05BD3)..........................................................................................3-1 RAM (MC68HC705BD3/MC68HC05BD5).............................................................3-1 ROM (MC68HC05BD3) .........................................................................................3-2 ROM (MC68HC05BD5) .........................................................................................3-2 EPROM (MC68HC705BD3) ..................................................................................3-2 Bootstrap ROM ......................................................................................................3-2
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4 RESETS AND INTERRUPTS
4.1 RESETS ................................................................................................................4-1 4.1.1 Power-On Reset (POR) ...................................................................................4-1 4.1.2 RESET Pin.......................................................................................................4-1 4.1.3 Illegal Address (ILADR) Reset.........................................................................4-2 4.1.4 Computer Operating Properly (COP) Reset ....................................................4-2 4.2 INTERRUPTS........................................................................................................4-3 4.2.1 Non-maskable Software Interrupt (SWI) ..........................................................4-3 4.2.2 Maskable Hardware Interrupts.........................................................................4-5 4.2.2.1 External Interrupt (IRQ)..............................................................................4-5 4.2.2.2 Sync Signal Processor Interrupt.................................................................4-7 4.2.2.3 M-Bus Interrupts.........................................................................................4-7 4.2.2.4 Multi-Function Timer Interrupts ..................................................................4-8
5 MULTI-FUNCTION TIMER
5.1 5.2 5.3 MFT Counter Register ...........................................................................................5-1 MFT Control and Status Register ..........................................................................5-1 COP Watchdog......................................................................................................5-2
6 PULSE WIDTH MODULATION
6.1 6.2 PWM Registers .....................................................................................................6-1 General Operation .................................................................................................6-1
7 M-BUS SERIAL INTERFACE
7.1 M-Bus Interface Features ......................................................................................7-1 7.2 M-Bus Protocol ......................................................................................................7-2 7.2.1 START Signal...................................................................................................7-3 7.2.2 Slave Address Transmission ............................................................................7-3 7.2.3 Data Transfer....................................................................................................7-4 7.2.4 Repeated START Signal ..................................................................................7-4 7.2.5 STOP Signal ....................................................................................................7-4 7.2.6 Arbitration Procedure .......................................................................................7-4 7.2.7 Clock Synchronization .....................................................................................7-5 7.2.8 Handshaking....................................................................................................7-5 7.3 M-Bus Registers ....................................................................................................7-5
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7.3.1 M-Bus Address Register (MADR) ....................................................................7-6 7.3.2 M-Bus Frequency Register (MFDR).................................................................7-6 7.3.3 M-Bus Control Register (MCR) ........................................................................7-7 7.3.4 M-Bus Status Register (MSR)..........................................................................7-8 7.3.5 M-Bus Data I/O Register (MDR) ......................................................................7-9 7.4 Programming Considerations ................................................................................7-11 7.4.1 Initialization ......................................................................................................7-11 7.4.2 Generation of a START Signal and the First Byte of Data Transfer..................7-11 7.4.3 Software Responses after Transmission or Reception of a Byte .....................7-11 7.4.4 Generation of the STOP Signal........................................................................7-12 7.4.5 Generation of a Repeated START Signal ........................................................7-13 7.4.6 Slave Mode ......................................................................................................7-13 7.4.7 Arbitration Lost .................................................................................................7-13
8 SYNC SIGNAL PROCESSOR
8.1 Functional Blocks...................................................................................................8-1 8.1.1 Polarity Correction............................................................................................8-1 8.1.1.1 Separate Vertical Sync Input ......................................................................8-2 8.1.1.2 Separate Horizontal Or Composite Sync Input ..........................................8-3 8.1.2 Sync Detection.................................................................................................8-3 8.1.3 Free-running Pseudo Sync Signal Generator ..................................................8-4 8.1.4 Sync Separation...............................................................................................8-4 8.1.5 Vertical Sync Pulse Reshaper..........................................................................8-5 8.1.6 Sync Signal Counters ......................................................................................8-5 8.2 VSYNC Interrupt....................................................................................................8-5 8.3 Registers ...............................................................................................................8-7 8.3.1 Sync Signal Control & Status Register (SSCSR).............................................8-7 8.3.2 Vertical Frequency Registers (VFRS) ..............................................................8-9 8.3.3 Line Frequency Registers (LFRs) ....................................................................8-9 8.3.4 Sync Signal Control Register (SSCR)..............................................................8-10 8.3.5 Horizontal Sync Period Width Register (HPWR)..............................................8-10 8.4 System Operation ..................................................................................................8-11
9 CPU CORE AND INSTRUCTION SET
9.1 Registers ...............................................................................................................9-1 9.1.1 Accumulator (A) ...............................................................................................9-1 9.1.2 Index register (X)..............................................................................................9-2 9.1.3 Program counter (PC) ......................................................................................9-2 9.1.4 Stack pointer (SP) ............................................................................................9-2 9.1.5 Condition code register (CCR).........................................................................9-2
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9.2 Instruction set ........................................................................................................9-3 9.2.1 Register/memory Instructions ..........................................................................9-4 9.2.2 Branch instructions ..........................................................................................9-4 9.2.3 Bit manipulation instructions ............................................................................9-4 9.2.4 Read/modify/write instructions.........................................................................9-4 9.2.5 Control instructions ..........................................................................................9-4 9.2.6 Tables...............................................................................................................9-4 9.3 Addressing modes.................................................................................................9-11 9.3.1 Inherent............................................................................................................9-11 9.3.2 Immediate ........................................................................................................9-11 9.3.3 Direct ...............................................................................................................9-11 9.3.4 Extended..........................................................................................................9-12 9.3.5 Indexed, no offset ............................................................................................9-12 9.3.6 Indexed, 8-bit offset .........................................................................................9-12 9.3.7 Indexed, 16-bit offset .......................................................................................9-12 9.3.8 Relative ............................................................................................................9-13 9.3.9 Bit set/clear ......................................................................................................9-13 9.3.10 Bit test and branch...........................................................................................9-13
10 LOW POWER MODES
10.1 10.2 10.3 STOP Mode.........................................................................................................10-1 WAIT Mode..........................................................................................................10-1 COP Watchdog Timer Considerations.................................................................10-2
11 OPERATING MODES
11.1 11.2 11.3 User Mode (Normal Operation) ...........................................................................11-2 Self-Check Mode .................................................................................................11-2 Bootstrap Mode ...................................................................................................11-4
12 ELECTRICAL SPECIFICATIONS
12.1 12.2 12.3 12.4 12.5 12.6 Maximum Ratings................................................................................................12-1 Thermal Characteristics ......................................................................................12-1 DC Electrical Characteristics...............................................................................12-2 Control Timing .....................................................................................................12-3 M-Bus Timing ......................................................................................................12-4 Sync Signal Processor Timing.............................................................................12-5
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13 MECHANICAL SPECIFICATIONS
13.1 13.2 42-Pin SDIP Package (Case 858-01) ..................................................................13-1 40-Pin DIP Package (Case 711-03).....................................................................13-1
14 MC68HC705BD3
14.1 14.2 14.3 14.3.1 14.3.2 14.4 Features...............................................................................................................14-1 Memory Map........................................................................................................14-1 EPROM Programming .........................................................................................14-1 Programming Control Register (PCR)............................................................14-3 EPROM Programming Sequence ..................................................................14-3 DC Electrical Characteristics ...............................................................................14-4
15 MC68HC05BD5
15.1 15.2 15.3 Features...............................................................................................................15-1 Memory Map........................................................................................................15-1 DC Electrical Characteristics ...............................................................................15-3
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MC68HC05BD3
LIST OF FIGURES
Figure Number 1-1 2-1 2-2 2-3 3-1 4-1 4-2 4-3 6-1 7-1 7-2 7-3 7-4 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 10-1 11-1 11-2 11-3 12-1 14-1 15-1 TITLE Page Number
MC68HC05BD3/MC68HC705BD3/MC68HC05BD5 Block Diagram ......................1-2 Pin Assignment for 40-pin DIP Package.................................................................2-2 Pin Assignment for 42-pin SDIP Package ..............................................................2-3 Parallel Port I/O Circuitry ........................................................................................2-6 Memory Map ..........................................................................................................3-3 Power-On Reset and RESET Timing......................................................................4-2 Interrupt Stacking Order .........................................................................................4-4 External Interrupt Circuit and Timing ......................................................................4-6 8-Bit PWM Output Waveforms................................................................................6-2 M-Bus Interface Block Diagram ..............................................................................7-2 M-Bus Transmission Signal Diagram ......................................................................7-3 Clock Synchronization ............................................................................................7-5 Flowchart of M-Bus Interrupt Routine.....................................................................7-10 Sync Signal Processor Block Diagram ...................................................................8-2 Sync Signal Polarity Correction ..............................................................................8-3 Sync Separator.......................................................................................................8-4 Sync Signal Counters Block Diagram.....................................................................8-6 Vertical Frequency Counter Timing ........................................................................8-6 Typical Monitor System Operation..........................................................................8-12 Programming model ...............................................................................................9-1 Stacking order ........................................................................................................9-2 WAIT Flowchart ....................................................................................................10-2 Flowchart of Mode Entering .................................................................................11-1 Self-Check Mode Timing ......................................................................................11-2 MC68HC05BD3 Self-Test Circuit..........................................................................11-3 M-Bus Timing........................................................................................................12-4 MC68HC705BD3 Memory Map............................................................................14-2 MC68HC05BD5 Memory Map..............................................................................15-2
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MC68HC05BD3
LIST OF TABLES
Table Number 2-1 2-2 3-1 4-1 5-1 7-1 8-1 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 11-1 11-2 12-1 12-2 12-3 12-4 12-5 14-1 14-2 15-1 TITLE Page Number
I/O Pin Functions ....................................................................................................2-4 Configuration for PC6 and PC7 ..............................................................................2-5 Register Outline......................................................................................................3-4 Reset/Interrupt Vector Addresses ..........................................................................4-4 COP Reset and RTI Rates .....................................................................................5-3 M-Bus Prescaler .....................................................................................................7-6 Vertical Frame Frequencies ....................................................................................8-9 MUL instruction.......................................................................................................9-5 Register/memory instructions.................................................................................9-5 Branch instructions .................................................................................................9-6 Bit manipulation instructions...................................................................................9-6 Read/modify/write instructions ...............................................................................9-7 Control instructions.................................................................................................9-7 Instruction set .........................................................................................................9-8 M68HC05 opcode map...........................................................................................9-10 Mode Selection.....................................................................................................11-2 Self-Check Report ................................................................................................11-4 DC Electrical Characteristics for MC68HC05BD3 ................................................12-2 Control Timing ......................................................................................................12-3 M-Bus Interface Input Signal Timing.....................................................................12-4 M-Bus Interface Output Signal Timing..................................................................12-4 Sync Signal Processor Timing..............................................................................12-5 MC68HC705BD3 Programming Boards...............................................................14-1 DC Electrical Characteristics for MC68HC705BD3 ..............................................14-4 DC Electrical Characteristics for MC68HC05BD5 ................................................15-3
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MC68HC05BD3
1
1
GENERAL DESCRIPTION
The MC68HC05BD3 HCMOS microcontroller is a member of the M68HC05 Family of low-cost single-chip microcontrollers. This 8-bit microcontroller unit (MCU) contains an on-chip oscillator, CPU, RAM, ROM, parallel I/O capability with pins programmable as input or output, M-Bus serial interface system (I2C), Pulse Width Modulator, Multi-Function Timer, and Sync Signal Processor. These features make it particularly suitable as a multi-sync computer monitor MCU. The MC68HC05BD5 is functionally equivalent to MC68HC05BD3, with increase RAM and ROM. The MC68HC705BD3 is an EPROM version of the MC68HC05BD5. All references to the MC68HC05BD3 apply equally to the MC68HC705BD3 and MC68HC05BD5, unless otherwise stated. References specific to the MC68HC705BD3 are italicized in the text and also, for quick reference, they are summarized in Section 14. References to MC68HC05BD5 are summarized in Section 15.
1.1
* * * *
Features
Fully static chip design featuring the industry standard 8-bit M68HC05 core Power saving Wait mode 128 bytes of on-chip RAM for MC68HC05BD3 256 bytes for MC68HC705BD3 and MC68HC05BD5 3.75K-bytes of user ROM for MC68HC05BD3 7.75K-bytes of user ROM for MC68HC05BD5 7.75K-bytes of user EPROM for MC68HC705BD3 24 bidirectional I/O lines: 14 dedicated and 10 multiplexed I/O lines. 4 of the 14 dedicated I/O lines and 6 of the MUXed I/O lines have +10V open-drain O/Ps. 16 channels PWM outputs: 8 dedicated, +10V open-drain PWM channels and 8 multiplexed with I/O lines of which 6 of them have +10V open-drain outputs. M-Bus Serial Interface (I2C-bus) Multi-Function Timer (MFT) with Periodic Interrupt COP watchdog reset
* * * * *
I2C-bus is a proprietary Philips interface bus
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MC68HC05BD3
GENERAL DESCRIPTION
MOTOROLA 1-1
1
* * * Horizontal and Vertical Sync Signal Processor Self-check mode Available in 40-pin DIP and 42-pin SDIP packages
PORT A
USER ROM 3.75K-Bytes for MC68HC05BD3 7.75K-Bytes for MC68HC05BD5
DDR A
8
PA0 - PA7
7.75K-Bytes EPROM for MC68HC705BD3
RAM 128 Bytes for MC68HC05BD3 256 Bytes for MC68HC705BD3 & MC68HC05BD5 SELF-CHECK ROM - 224 Bytes for MC68HC05BD3 & MC68HC05BD5 only PORT B DDR B
4
PB0 PB1 PB2* - PB5*
BOOTSTRAP ROM - 480 Bytes for MC68HC705BD3 only
7 0 ACCUMULATOR 7 0
M68HC05 CPU
PWM
INDEX REGISTER 5 12 0000011 15 00 4 0 STACK POINTER 0
PWM0* PWM1* PWM2* PWM3* PWM4* PWM5* PWM6* PWM7* PC0/PWM8* PC1/PWM9* PC2/PWM10* PC3/PWM11* PC4/PWM12* PC5/PWM13* PC6/PWM14/VTTL PC7/PWM15/HTTL VSYNC HSYNC
PROGRAM COUNTER
IRQ/VPP RESET
RESET
7 0 111HINZC CONDITION CODE REGISTER
MFT (with COP)
SYNC SIGNAL PROCESSOR (SSP)
EXTAL XTAL VDD VSS
PORT D
DDR D
OSC /2
POWER
PORT C
DDR C
PD0/SDA PD1/SCL
M-BUS
* +10V open-drain +5V open-drain if the pin is configured as SDA or SCL
Figure 1-1 MC68HC05BD3/MC68HC705BD3/MC68HC05BD5 Block Diagram
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MOTOROLA 1-2
GENERAL DESCRIPTION
MC68HC05BD3
2
2
PIN DESCRIPTION AND I/O PORTS
This section provides a description of the functional pins and I/O programming of the MC68HC05BD3 microcontroller.
2.1
PIN NAME VDD, VSS
PIN DESCRIPTIONS
40-pin DIP PIN No. 5, 6 42-pin SDIP PIN No. 5, 7 DESCRIPTION Power is supplied to the MCU using these two pins. VDD is power and VSS is ground. In the user mode this pin an external hardware interrupt IRQ. It is software programmable to provide two choices of interrupt triggering sensitivity. These options are: 1) negative edge-sensitive triggering only, or 2) both negative edge-sensitive and level sensitive triggering. In the bootstrap mode on the MC68HC705BD3, this is the EPROM programming voltage input pin. The active low RESET input is not required for start-up, but can be used to reset the MCU internal state and provide an orderly software start-up procedure. These pins provide connections to the on-chip oscillator. The oscillator can be driven by a AT-crystal circuit or a ceramic resonator with a frequency of 4.2 MHz. EXTAL may also be driven by an external oscillator if an external crystal/resonator circuit is not used. See Figure 11-3 for values of crystal circuit external components. These eight I/O lines comprise port A. The state of any pin is software programmable. All port A lines are configured as input during power on or external reset. These six I/O lines comprise port B. The state of any pin is software programmable. All port B lines are configured as input during power on or external reset. PB2 to PB5 are +10V open-drain pins. These six port C pins are +10V open-drain type. The state of any pin is software programmable. All port C lines are configured as input during power on or external reset. These pins become PWM output channels 8 to 13 by setting the appropriate bits in Configuration register 1 ($0A).
IRQ/VPP
15
16
RESET
4
4
XTAL, EXTAL
7, 8
8, 9
PA0-PA7
23-16
24-17
PB0-PB5
14-9
15-10
PC0/PWM8 to PC5/PWM13
26-31
27-32
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PIN DESCRIPTION AND I/O PORTS
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2
PIN NAME PC6/PWM14/VTTL, PC7/PWM15/HTTL PD0/SDA, PD1/SCL PWM0 to PWM7
40-pin DIP PIN No. 32, 33
42-pin SDIP PIN No. 33, 34
DESCRIPTION These two port C I/O lines are shared with the PWM and Sync Signal Processor. Configuration for use are set by the Configuration register 1 ($0A) and Configuration register 2 ($0B). These two port D I/O lines are shared with the M-Bus lines SDA and SCL. When configured as M-Bus lines in Configuration register 2 ($0B), these pins become +5V open-drain pins. These eight pins are dedicated for the 8-bit PWM channel 0 to 7. These two pins are for video sync signals input from the host computer. The polarity of the input signals can either be positive or negative. These two pins contain internal Schmitt triggers as part of their inputs to improve noise immunity
24, 25 3-1, 38-34
25, 26 3-1, 40-38, 36, 35 41, 42
HSYNC, VSYNC
39, 40
2.2
Pin Assignments
PWM2 PWM1 PWM0 RESET VDD VSS XTAL EXTAL PB5 PB4 PB3 PB2 PB1 PB0 IRQ/VPP PA7 PA6 PA5 PA4 PA3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSYNC HSYNC PWM3 PWM4 PWM5 PWM6 PWM7 PC7/PWM15/HTTL PC6/PWM14/VTTL PC5/PWM13 PC4/PWM12 PC3/PWM11 PC2/PWM10 PC1/PWM9 PC0/PWM8 PD1/SCL PD0/SDA PA0 PA1 PA2
Figure 2-1 Pin Assignment for 40-pin DIP Package
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PIN DESCRIPTION AND I/O PORTS
MC68HC05BD3
PWM2 PWM1 PWM0 RESET VDD NC VSS XTAL EXTAL PB5 PB4 PB3 PB2 PB1 PB0 IRQ/VPP PA7 PA6 PA5 PA4 PA3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSYNC HSYNC PWM3 PWM4 PWM5 NC PWM6 PWM7 PC7/PWM15/HTTL PC6/PWM14/VTTL PC5/PWM13 PC4/PWM12 PC3/PWM11 PC2/PWM10 PC1/PWM9 PC0/PWM8 PD1/SCL PD0/SDA PA0 PA1 PA2
2
Figure 2-2 Pin Assignment for 42-pin SDIP Package
2.3
INPUT/OUTPUT PORTS
In the User Mode there are 24 bidirectional I/O lines arranged as 4 I/O ports (Port A, B, C, and D). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs). Also, if enabled by software, Port C and D will have additional functions as PWM outputs, M-Bus I/O and Sync Signal Processor outputs.
2.3.1
Port A
Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The Port A data register is at $00 and the data direction register (DDR) is at $04. Reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
2.3.2
Port B
Port B is a 6-bit bidirectional port which does not share any of its pins with other subsystems. PB2 to PB5 are +10V open-drain port pins. The Port B data register is at $01 and the data direction register (DDR) is at $05. Reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
TPG
MC68HC05BD3
PIN DESCRIPTION AND I/O PORTS
MOTOROLA 2-3
2.3.3
Port C
2
Port C is an 8-bit bidirectional port which shares pins with PWM and SSP subsystem. See Section 6 for a detailed description of PWM and Section 8 for a detailed description of SSP. These pins are configured to PWM output when the corresponding bits in the Configuration register 1 are set, except PC6 and PC7. PC6 and PC7 are configured to SSP outputs when the corresponding bits in the Configuration register 2 are set. The Port C data register is at $02 and the data direction register (DDR) is at $06. Reset does not affect the data register, but clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
2.3.4
Port D
Port D is a 2-bit bidirectional port which shares pins with M-Bus subsystem. See Section 7 for a detailed description of M-Bus. These pins are configured to the corresponding functions when the corresponding bits in the Configuration register 2 are set. They are +5V open-drain I/O pins when used as M-Bus I/O. The Port D data register is at $03 and the data direction register (DDR) is at $07. Reset does not affect the data register, yet clears the data direction register, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode.
2.3.5
Input/Output Programming
Bidirectional port lines may be programmed as an input or an output under software control. The direction of the pins is determined by the state of the corresponding bit in the port data direction register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if its corresponding DDR bit is set. A pin is configured as an input if its corresponding DDR bit is cleared. During Reset, all DDRs are cleared, which configure all port pins as inputs. The data direction registers are capable of being written to or read by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin.
Table 2-1 I/O Pin Functions
R/W 0 0 1 1 DDR 0 1 0 1 I/O Pin Function The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in an output mode. The output data latch is read.
TPG
MOTOROLA 2-4
PIN DESCRIPTION AND I/O PORTS
MC68HC05BD3
2.3.6
Port C and D Configuration Registers
Port C and Port D are shared with PWM, M-Bus and SSP. The configuration registers at $0A and $0B are used to configure those I/O pins. They are default to zero after power-on reset. Setting these bits will set the corresponding pins to the corresponding functions, except PC6 and PC7. For example, setting SCL and SDA bits of register $0B will configure Port D pins 1 and 0 as M-Bus pins, regardless of DDR1 and DDR0 settings.
Address bit 7 Configuration Register 1 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset
2
$000A PWM15 PWM14 PWM13 PWM12 PWM11 PWM10 PWM9 PWM8 0000 0000 State on reset 0000 0000
Address bit 7 Configuration Register 2 $000B HTTL
bit 6 VTTL
bit 5
bit 4
bit 3
bit 2
bit 1 SCL
bit 0 SDA
PC7 and PC6 are shared with both PWM and SSP. When HTTL and VTTL in $000B are set, PC7 and PC6 are configured as HTTL and VTTL outputs respectively, regardless of the status of PWM15 and PWM14 in $000A. That is, HTTL and VTTL settings override PWM15 and PWM14 settings.
Table 2-2 Configuration for PC6 and PC7
PWM15 0 0 1 1 HTTL 0 1 0 1 Result of PC7 PC7 HTTL PWM15 HTTL PWM14 0 0 1 1 VTTL 0 1 0 1 Result of PC6 PC6 VTTL PWM14 VTTL
TPG
MC68HC05BD3
PIN DESCRIPTION AND I/O PORTS
MOTOROLA 2-5
2
INTERNAL MC68HC05 CONNECTIONS
DATA DIRECTION REGISTER BIT
LATCHED OUTPUT DATA BIT
OUTPUT
I/O PIN
INPUT REGISTER BIT
INPUT I/O
(a)
7 6 5 4 3 2 1 0
TYPICAL PORT DATA DIRECTION REGISTER
DDR 7
DDR 6
DDR 5
DDR 4
DDR 3
DDR 2
DDR 1
DDR 0
TYPICAL PORT REGISTER I/O PORT LINES
Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0
(b)
VDD NOTE: (1) IP = INPUT PROTECTION (2) LATCH-UP PROTECTION NOT SHOWN
PORT DATA
&
PORT DDR
P
PAD
+
N IP
INTERNAL LOGIC
(c)
Figure 2-3 Parallel Port I/O Circuitry
TPG
MOTOROLA 2-6
PIN DESCRIPTION AND I/O PORTS
MC68HC05BD3
3
MEMORY AND REGISTERS
The MC68HC05BD3/MC68HC705BD3/MC68HC05BD5 has a 16K-byte memory map consisting of registers, user ROM/EPROM, user RAM, self-check/bootstrap ROM, and I/O as shown in Figure 3-1.
3
3.1
Registers
All the I/O, control and status registers of the MC68HC05BD3 are contained within the first 48-byte block of the memory map (address $0000 to $002F).
3.2
RAM (MC68HC05BD3)
The user RAM consists of 128 bytes of memory, from $0080 to $00FF. This is shared with a 64 byte stack area. The stack begins at $00FF and counts down to $00C0.
3.3
RAM (MC68HC705BD3/MC68HC05BD5)
The user RAM consists of 256 bytes of memory, from $0080 to $017F. This is shared with a 64 byte stack area. The stack begins at $00FF and counts down to $00C0.
Note:
Using the stack area for data storage or temporary work locations requires care to prevent the data from being overwritten due to stacking from an interrupt or subroutine call.
TPG
MC68HC05BD3
MEMORY AND REGISTERS
MOTOROLA 3-1
3.4
ROM (MC68HC05BD3)
The user ROM consists of 3.75K-bytes of memory, from $3000 to $3EFF.
3
3.5
ROM (MC68HC05BD5)
The user ROM consists of 7.75K-bytes of memory, from $2000 to $3EFF.
3.6
EPROM (MC68HC705BD3)
The user EPROM consists of 7.75K-bytes of memory, from $2000 to $3EFF.
3.7
Bootstrap ROM
This is available on the MC68HC705BD3 device only. It stores the on-chip program for programming the user EPROM.
TPG
MOTOROLA 3-2
MEMORY AND REGISTERS
MC68HC05BD3
MC68HC05BD3 $0000 $002F $0030 I/O 48 Bytes $0000 $002F $0030
MC68HC05BD5 I/O 48 Bytes
MC68HC705BD3 $0000 $002F $0030 I/O 48 Bytes
Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register MFT Control and Status Register MFT Timer Counter Register Configuration Register 1 Configuration Register 2 SSP Control and Status Register Vertical Frequency High Register Vertical Frequency Low Register Line Frequency High Register Line Frequency Low Register Sync Signal Control Register Unused Unused Unused Unused Unused MBUS Address Register MBUS Frequency Divider Register MBUS Control Register MBUS Status Register MBUS Data Register Unused Programming Control Register HSYNC Period Width Register Reserved PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 PWM14 PWM15 $3FF0 $3FF2 $3FF4 $3FF6 $3FF8 $3FFA $3FFC $3FFE Reserved Reserved MFT MBUS SSP IRQ SWI RESET $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F
Unused $007F $0080 $00C0 $00FF $0100 User RAM 128 Bytes
Stack 64 Bytes
Unused $007F $0080 $00C0 $00FF
Stack 64 Bytes
Unused $007F $0080 $00C0 $00FF
Stack 64 Bytes
3
User RAM 256 Bytes $017F $0180
User RAM 256 Bytes $017F $0180
Unused
Unused
Unused
$1DFF $1E00 Bootstrap ROM 480 Bytes $1FDF $1FE0 $1FFF $2000
$1FFF $2000
Unused
$2FFF $3000
User ROM 7936 Bytes User ROM 3840 Bytes
User EPROM 7936 Bytes
$3EFF $3F00
Self-Check Program 224 Bytes Self-Check Vectors 16 Bytes User Vectors 16 Bytes
$3EFF $3F00
Self-Check Program 224 Bytes Self-Check Vectors 16 Bytes User Vectors 16 Bytes
$3EFF $3F00 Unused $3FDF $3FE0 $3FEF $3FF0 $3FFF Bootstrap Vectors 16 Bytes User Vectors 16 Bytes
$3FDF $3FE0 $3FEF $3FF0 $3FFF
$3FDF $3FE0 $3FEF $3FF0 $3FFF
Figure 3-1 Memory Map
TPG
MC68HC05BD3
MEMORY AND REGISTERS
MOTOROLA 3-3
Table 3-1 Register Outline
3
Register Name Port A data Port B data Port C data Port D data Port A data direction Port B data direction Port C data direction Port D data direction MFT control and status MFT timer counter Configuration 1 Configuration 2 SSP control and status Vertical frequency high Vertical frequency low Line frequency high Line frequency low Sync signal control Unused Unused Unused Unused Unused MBUS address MBUS frequency divider MBUS control MBUS status MBUS data Unused Programming Control HSYNC period width Reserved
Address bit 7 $0000 $0001 $0002 $0003 PC7 PA7
bit 6 PA6
bit 5 PA5 PB5
bit 4 PA4 PB4 PC4
bit 3 PA3 PB3 PC3
bit 2 PA2 PB2 PC2
bit 1 PA1 PB1 PC1 PD1
bit 0 PA0 PB0 PC0 PD0
State on reset undefined undefined undefined undefined
PC6
PC5
$0004 DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0000 0000 $0005 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 --00 0000
$0006 DDRC7 DDRC6 DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 0000 0000 $0007 $0008 TOF RTIF TOFIE RTIE IRQN DDRD1 DDRD0 RT1 RT0 ---- --00 0000 0-11
$0009 MFTCR7 MFTCR6 MFTCR5 MFTCR4 MFTCR3 MFTCR2 MFTCR1 MFTCR0 0000 0000 $000A PWM15 PWM14 PWM13 PWM12 PWM11 PWM10 PWM9 PWM8 0000 0000 $000B $000C $000D $000E HTTL VTTL SCL SDA VSIN VF8 VF0 LF8 LF0 0 00-- --00 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
VPOL HPOL VDET HDET SOUT INSRTB FOUT 0 VF7 0 VF6 0 LF6 0 0 VF5 0 LF5 0 VF12 VF4 0 LF4 0 VF11 VF3 LF11 LF3 0 VF10 VF2 LF10 LF2 0 VF9 VF1 LF9 LF1 0
$000F HOVER $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D MEN MCF MD7 LF7 VSIE
MAD7 MAD6 MAD5 MAD4 MAD3 MAD2 MAD1 FD4 MIEN MASS MD6 MSTA MBB MD5 MTX MAL MD4 MD3 FD3 TXAK SRW MD2 MIF MD1 FD2 FD1 FD0
0000 000---0 0000 0000 0--RXAK 1000 -001 MD0 undefined
ELAT
PGM
---- --00
$001E HPWR7 HPWR6 HPWR5 HPWR4 HPWR3 HPWR2 HPWR1 HPWR0 0000 0000 $001F
TPG
MOTOROLA 3-4
MEMORY AND REGISTERS
MC68HC05BD3
Table 3-1 Register Outline
Register Name 0PWM 1PWM 2PWM 3PWM 4PWM 5PWM 6PWM 7PWM 8PWM 9PWM 10PWM 11PWM 12PWM 13PWM 14PWM 15PWM
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State on reset
$0020 0PWM4 0PWM3 0PWM2 0PWM1 0PWM0 0BRM2 0BRM1 0BRM0 0000 0000 $0021 1PWM4 1PWM3 1PWM2 1PWM1 1PWM0 1BRM2 1BRM1 1BRM0 0000 0000 $0022 2PWM4 2PWM3 2PWM2 2PWM1 2PWM0 2BRM2 2BRM1 2BRM0 0000 0000 $0023 3PWM4 3PWM3 3PWM2 3PWM1 3PWM0 3BRM2 3BRM1 3BRM0 0000 0000 $0024 4PWM4 4PWM3 4PWM2 4PWM1 4PWM0 4BRM2 4BRM1 4BRM0 0000 0000 $0025 5PWM4 5PWM3 5PWM2 5PWM1 5PWM0 5BRM2 5BRM1 5BRM0 0000 0000 $0026 6PWM4 6PWM3 6PWM2 6PWM1 6PWM0 6BRM2 6BRM1 6BRM0 0000 0000 $0027 7PWM4 7PWM3 7PWM2 7PWM1 7PWM0 7BRM2 7BRM1 7BRM0 0000 0000 $0028 8PWM4 8PWM3 8PWM2 8PWM1 8PWM0 8BRM2 8BRM1 8BRM0 0000 0000 $0029 9PWM4 9PWM3 9PWM2 9PWM1 9PWM0 9BRM2 9BRM1 9BRM0 0000 0000 $002A 10PWM4 10PWM3 10PWM2 10PWM1 10PWM0 10BRM2 10BRM1 10BRM0 0000 0000 $002B 11PWM4 11PWM3 11PWM2 11PWM1 11PWM0 11BRM2 11BRM1 11BRM0 0000 0000 $002C 12PWM4 12PWM3 12PWM2 12PWM1 12PWM0 12BRM2 12BRM1 12BRM0 0000 0000 $002D 13PWM4 13PWM3 13PWM2 13PWM1 13PWM0 13BRM2 13BRM1 13BRM0 0000 0000 $002E 14PWM4 14PWM3 14PWM2 14PWM1 14PWM0 14BRM2 14BRM1 14BRM0 0000 0000 $002F 15PWM4 15PWM3 15PWM2 15PWM1 15PWM0 15BRM2 15BRM1 15BRM0 0000 0000
3
TPG
MC68HC05BD3
MEMORY AND REGISTERS
MOTOROLA 3-5
3
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA 3-6
MEMORY AND REGISTERS
MC68HC05BD3
4
RESETS AND INTERRUPTS
4.1 RESETS
4
The MC68HC05BD3 can be reset in four ways: by the initial power-on reset function, by an active low input to the RESET pin, by an opcode fetch from an illegal address, and by a COP watchdog timer reset. Any of these resets will cause the program to go to its starting address, specified by the contents of memory locations $3FFE and $3FFF, and cause the interrupt mask of the Condition Code register to be set.
4.1.1
Power-On Reset (POR)
The power-on reset occurs when a positive transition is detected on the supply voltage, VDD. The power-on reset is used strictly for power-up conditions, and should not be used to detect any drops in the power supply voltage. There is no provision for a power-down reset. The power-on circuitry provides for a 4064 tcyc delay from the time that the oscillator becomes active. If the external RESET pin is low at the end of the 4064 tcyc time out, the processor remains in the reset condition until RESET goes high. The user must ensure that VDD has risen to a point where the MCU can operate properly prior to the time the 4064 POR cycles have elapsed. If there is doubt, the external RESET pin should remain low until such time that VDD has risen to the minimum operating voltage specified.
4.1.2
RESET Pin
The RESET input pin is used to reset the MCU to provide an orderly software start-up procedure. When using the external reset, the RESET pin must stay low for a minimum of 1.5tcyc. The RESET pin contains an internal Schmitt Trigger as part of its input to improve noise immunity.
TPG
MC68HC05BD3
RESETS AND INTERRUPTS
MOTOROLA 4-1
t
VDDR
VDD VDD THRESHOLD (TYPICALLY 1-2V)
XTAL PIN1
4
INTERNAL CLOCK2 INTERNAL ADDRESS BUS2
toxov tcyc
4064 tcyc
3FFE
3FFF
NEW PC
3FFE
3FFE
3FFF
NEW PC
INTERNAL DATA BUS2
NEW PCL
NEW PCH
OP CODE tRL =1.5tCYC
3
PCH
PCL
OP CODE
RESET
NOTES: 1. XTAL is not meant to represent frequency. It is only used to represent time. 2. Internal clock, internal address bus, and internal data bus signals are not available externally. 3. Next rising edge of internal clock after rising edge of RESET initiates reset sequence.
Figure 4-1 Power-On Reset and RESET Timing
4.1.3
Illegal Address (ILADR) Reset
The MCU monitors all opcode fetches. If an illegal address space is accessed during an opcode fetch, an internal reset is generated. Illegal address spaces consist of all unused locations within the memory map and the I/O registers (see Figure 3-1). Because the internal reset signal is used, the MCU comes out of an ILADR reset in the same operating mode it was in when the opcode was fetched.
4.1.4
Computer Operating Properly (COP) Reset
The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific amount of time by a program reset sequence.
TPG
MOTOROLA 4-2
RESETS AND INTERRUPTS
MC68HC05BD3
Note:
COP time-out is prevented by periodically writing a "0" to bit 0 of address $3FF0.
If the watchdog timer is allowed to time-out, an internal reset is generated to reset the MCU. Because the internal reset signal is used, the MCU comes out of a COP reset in the same operating mode it was in when the COP time-out was generated. The COP reset function is always enabled. See Section 5.3 for more information on the COP watchdog timer.
4
4.2 INTERRUPTS
The MCU can be interrupted by different sources - four maskable hardware interrupt and one non-maskable software interrupt: * * * * * External signal on the IRQ pin Multi-Function Timer (MFT) M-Bus Interface (MBUS) Sync Signal Processor (SSP) Software Interrupt Instruction (SWI)
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are disabled. Clearing the I-bit enables interrupts. Interrupts cause the processor to save the register contents on the stack and to set the interrupt mask (I-bit) to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume. Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I-bit clear) the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. Table 4-1 shows the relative priority of all the possible interrupt sources.
4.2.1
Non-maskable Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-maskable interrupt: it is execute regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupt enabled), SWI is executed after interrupts that were pending when the SWI was fetched, but before interrupts generated after the SWI was fetched. The SWI interrupt service routine address is specified by the contents of memory locations $3FFC and $3FFD.
TPG
MC68HC05BD3
RESETS AND INTERRUPTS
MOTOROLA 4-3
$00C0 (BOTTOM OF STACK) $00C1 UNSTACKING ORDER $00C2 * * * 5 4 3 2 1 1 2 3 4 5 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PROGRAM COUNTER (HIGH BYTE) PROGRAM COUNTER (LOW BYTE) * * STACKING ORDER * * * * $00FD $00FE $00FF (TOP OF STACK) * * *
4
Figure 4-2 Interrupt Stacking Order
Table 4-1 Reset/Interrupt Vector Addresses
Register - - - SSCR MSR MFTCSR - - Flag Name - - - - MIF TOF RTIF - - Interrupt Reset Software External Interrupt VSYNC M-Bus Timer Overflow Real Time Interrupt - - CPU Interrupt RESET SWI IRQ SSP MBUS MFT - - Vector Address $3FFE-$3FFF $3FFC-$3FFD $3FFA-$3FFB $3FF8-$3FF9 $3FF6-$3FF7 $3FF4-$3FF5 $3FF2-$3FF3 $3FF0-$3FF1 Priority highest
lowest
TPG
MOTOROLA 4-4
RESETS AND INTERRUPTS
MC68HC05BD3
4.2.2
Maskable Hardware Interrupts
If the interrupt mask bit (I-bit) of the CCR is set, all maskable interrupts (internal and external) are masked. Clearing the I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit is cleared.
4
4.2.2.1
External Interrupt (IRQ)
The external interrupt IRQ can be software configured for "negative-edge" or "negative-edge and level" sensitive triggering by the IRQN bit in the Multi-Function TImer Control and Status register.
Address bit 7 MFT Control and Status $0008 TOF bit 6 RTIF bit 5 TOFIE bit 4 RTIE bit 3 IRQN bit 2 bit 1 RT1 bit 0 RT0 State on reset 0000 0-11
IRQN 1 (set) - Negative edge triggering for IRQ only Level and negative edge triggering for IRQ
0 (clear) -
When the signal of the external interrupt pin, IRQ, satisfies the condition selected, an external interrupt occurs. The actual processor interrupt is generated only if the interrupt mask bit of the condition code register is also cleared. When the interrupt is recognized, the current state of the processor is pushed onto the stack and the interrupt mask bit in the condition code register is set. This masks further interrupts until the present one is serviced. The service routine address is specified by the contents $3FFA & $3FFB. The interrupt logic recognizes negative edge transitions and pulses (special case of negative edges) on the external interrupt line. Figure 4-3 shows both a block diagram and timing for the interrupt line (IRQ) to the processor. The first method is used if pulses on the interrupt line are spaced far enough apart to be serviced. The minimum time between pulses is equal to the number of cycles required to execute the interrupt service routine plus 21 cycles. Once a pulse occurs, the next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The second configuration shows several interrupt lines wired-OR to perform the interrupt at the processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is recognized.
Note:
The internal interrupt latch is cleared in the first part of the service routine; therefore, one (and only one) external interrupt pulse could be latched during tILIL and serviced as soon as the I bit is cleared.
TPG
MC68HC05BD3
RESETS AND INTERRUPTS
MOTOROLA 4-5
IRQN bit
& +
VDD
&
4
IRQ pin
External Interrupt Request
D C
Q
I BIT (CCR)
Q R Power-On Reset
+
External Reset External Interrupt being serviced (read of vectors)
(a) Interrupt Function Diagram
EDGE SENSITIVE TRIGGER CONDITION IRQ tILIH tILIL The minimum pulse width tILIH is one internal bus period. The period tILIL should not be less than the number of tCYC cycles it takes to execute the interrupt service routine plus 21 tcyc cycles.
tILIL
LEVEL SENSITIVE TRIGGER CONDITION If after servicing an interrupt the IRQ pin remains low, then the next interrupt is recognized. Normally used with wired OR connection. Normally used with pull-up resistors for wired-OR connection.
Wired ORed Interrupt signals
IRQ
(b) Interrupt Mode Diagram
Figure 4-3 External Interrupt Circuit and Timing
TPG
MOTOROLA 4-6
RESETS AND INTERRUPTS
MC68HC05BD3
4.2.2.2
Sync Signal Processor Interrupt
The VSYNC interrupt is generated by the Sync Signal Processor (SSP) after a vertical sync pulse is detected as described in Section 8. The interrupt enable bit, VSIE, for the VSYNC interrupt is located at bit 7 of Sync Signal Control register (SSCR) at $0011. The I-bit in the CCR must be cleared in order for the VSYNC interrupt to be enabled. This interrupt will vector to the interrupt service routine located at the address specified by the contents of $3FF8 and $3FF9. The VSYNC interrupt latch will be cleared automatically by fetching of these vectors. Refer to Section 8 for detailed description of Sync Signal Processor.
4
4.2.2.3
M-Bus Interrupts
M-Bus interrupt is enabled when the M-Bus Interrupt Enable bit (MIEN) of M-Bus Control register is set, provided the interrupt mask bit of the Condition Code register is cleared. The interrupt service routine address is specified by the contents of memory location $3FF6 and $3FF7.
Address bit 7 M-Bus Status Register $001A MCF bit 6 MAAS bit 5 MBB bit 4 MAL bit 3 bit 2 SRW bit 1 MIF bit 0 State on reset
RXAK 1000 0001
MIF - M-Bus Interrupt 1 (set) - An M-Bus interrupt has occurred. An M-Bus interrupt has not occurred.
0 (clear) -
When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one of the following events occurs: 1) Completion of one byte of data transfer. It is set at the falling edge of the 9th clock - MCF set. 2) A match of the calling address with its own specific address in slave mode MAAS set. 3) A loss of bus arbitration - MAL set. This bit must be cleared by software in the interrupt routine. MCF - Data Transfer Complete 1 (set) - A byte transfer has been completed. A byte is being transfer.
0 (clear) -
MAAS - Addressed as Slave 1 (set) - Currently addressed as a slave. Not currently addressed.
TPG
0 (clear) -
MC68HC05BD3
RESETS AND INTERRUPTS
MOTOROLA 4-7
Then CPU needs to check the SRW bit and set its MTX bit accordingly. Writing to the M-Bus Control register clears this bit. MAL - Arbitration Lost 1 (set) - Lost arbitration in master mode. No arbitration lost.
0 (clear) -
4
Refer to Section 7 for detailed description of M-Bus Interface.
4.2.2.4
Multi-Function Timer Interrupts
There are two interrupt sources, TOF and RTIF bits of Multi-Function Timer Control and Status Register. The interrupt service routine address is specified by the contents of memory location $3FF4 and $3FF5.
Address bit 7 MFT Control and Status Register $0008 TOF bit 6 RTIF bit 5 TOFIE bit 4 RTIE bit 3 IRQN bit 2 bit 1 RT1 bit 0 RT0 State on reset 0000 0011
TOF - Timer Overflow 1 (set) - 8-bit ripple timer overflow has occurred. No 8-bit ripple timer overflow has occurred.
0 (clear) -
This bit is set when the 8-bit ripple counter overflows from $FF to $00; a timer overflow interrupt will occur, if TOFIE is set. TOF is cleared by writing a "0" to the bit. RTIF - Real Time Interrupt Flag 1 (set) - A real time interrupt has occurred. A real time interrupt has not occurred.
0 (clear) -
The clock frequency that drives the RTI circuit is E/16384, giving a maximum interrupt period of 8.19ms at a bus clock rate of 2MHz. A CPU interrupt request will be generated if RTIE is set. RTIF is cleared by writing a "0" to the bit. Refer to Section 5 for detailed description of Multi-Function Timer.
TPG
MOTOROLA 4-8
RESETS AND INTERRUPTS
MC68HC05BD3
5
MULTI-FUNCTION TIMER
The MFT provides miscellaneous functions to the MC68HC05BD3 MCU. It includes a timer overflow function, real-time interrupt, and COP watchdog. The external interrupt (IRQ) triggering option is also set by this module's MFT Control and Status Register. The clock base for this module is derived from the bus clock divided by four. For a 2MHz E (CPU) clock, the clock base is 0.5MHz. This clock base is then divided by an 8-stage ripple counter to generate the timer overflow. Timer overflow rate is thus E/1024. The output of this 8-stage ripple counter then drives a 4-stage divider to generate real time interrupt. Hence, the clock base for real time interrupt is E/16384. Real time interrupt rate is selected by RT0 and RT1 bits of MFT Control and Status register. The interrupt rates are E/16384, (E/16384)/2, (E/16384)/4, and (E/16384)/8. The selected real time interrupt rate is then divided by 8 to generate COP reset.
5
5.1
MFT Counter Register
The MFT counter register (MFTCR) can be read at location $0009. It is cleared by reset.
5.2
MFT Control and Status Register
Address bit 7 bit 6 RTIF bit 5 TOFIE bit 4 RTIE bit 3 IRQN bit 2 bit 1 RT1 bit 0 RT0 State on reset 0000 0011
MFT Control and Status Register
$1C
TOF
Register bit definitions: TOF - Timer Overflow 1 (set) - 8-bit ripple timer overflow has occurred. No 8-bit ripple timer overflow has occurred.
0 (clear) -
TPG
MC68HC05BD3
MULTI-FUNCTION TIMER
MOTOROLA 5-1
This bit is set when the 8-bit ripple counter overflows from $FF to $00; a timer overflow interrupt will occur, if TOFIE (bit 5) is set. TOF is cleared by writing a "0" to the bit. RTIF - Real Time Interrupt Flag 1 (set) - A real time interrupt has occurred. A real time interrupt has not occurred.
0 (clear) -
When RTIF is set, a CPU interrupt request is generated if RITE is set. The clock frequency that drives the RTI circuit is E/16384 giving a maximum interrupt period of 8.19ms at a bus rate of 2MHz. RTIF is cleared by writing a "0" to the bit.
5
TOFIE - Timer Overflow Interrupt Enable 1 (set) - TOF interrupt is enabled. TOF interrupt is disabled.
0 (clear) -
RTIE - Real Time Interrupt Enable 1 (set) - Real time interrupt is enabled. Real time interrupt is disabled.
0 (clear) -
IRQN - IRQ Pin Trigger Option 1 (set) - Negative edge triggering for IRQ only Level and negative edge triggering for IRQ
0 (clear) -
RT1, RT0 - Rate Select for COP watchdog and RTI See Section 5.3 on watchdog reset.
5.3
COP Watchdog
The COP (Computer Operating Properly) watchdog timer function is implemented by using the output of the Multi-Function Timer counter. The minimum COP reset rates are controlled by RT0 and RT1 of MFT Control and Status register. If the COP circuit times out, an internal reset is generated and the reset vector is fetched (at $3FFE & $3FFF). Preventing a COP time-out is achieved by writing a "0" to bit 0 of address $3FF0. The COP counter has to be cleared periodically by software with a period less than COP reset rate. The COP watchdog timer is always enabled and continues to count in Wait mode.
TPG
MOTOROLA 5-2
MULTI-FUNCTION TIMER
MC68HC05BD3
Table 5-1 COP Reset and RTI Rates
Minimum COP reset period COP E clock = 2MHz E/16384/7/1 57.344ms E/16384/7/2 114.688ms E/16384/7/4 229.376ms E/16384/7/8 458.752ms RTI period RTI E clock = 2MHz E/16384/1 8.192ms E/16384/2 16.384ms E/16384/4 32.768ms E/16384/8 65.536ms
RT1 0 0 1 1
RT0 0 1 0 1
Note:
RT0 and RT1 should only be changed immediately after COP watchdog timer has been reset.
5
TPG
MC68HC05BD3
MULTI-FUNCTION TIMER
MOTOROLA 5-3
5
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA 5-4
MULTI-FUNCTION TIMER
MC68HC05BD3
6
PULSE WIDTH MODULATION
The MC68HC05BD3 has 16 PWM channels. Channel 0 to 7 are dedicated PWM channels. Channel 8 to 15 are shared with port C I/O pins, and are selected by the respective bits in Configuration register 1. PWM channels 0 to 13 are +10V open-drain type; therefore a pull-up resistor is required at each of the pins.
6
6.1 PWM Registers
Each PWM channel has an 8-bit register which contains a 5-bit PWM in the MSB portion and a 3-bit binary rate multiplier (BRM) in the LSB portion. The PWM channel data registers are located from $20 to $2F.
Address 0PWM : 15PWM $0020 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 0BRM2 bit 1 0BRM1 bit 0 0BRM0 State on reset 0000 0000
0PWM4 0PWM3 0PWM2 0PWM1 0PWM0 :
$002F 15PWM4 15PWM3 15PWM2 15PWM1 15PWM0 15BRM2 15BRM1 15BRM0
0000 0000
6.2
General Operation
The value programmed in the 5-bit PWM portion will determine the pulse length of the output. The clock to the 5-bit PWM portion is the E clock and the repetition rate of the output is hence 62.5KHz at 2MHz E clock. The 3-bit BRM will generate a number of narrow pulses which are equally distributed among an 8-PWM-cycle. The number of pulses generated is equal to the number programmed in the 3-bit BRM portion. Example of the waveforms are shown in Figure 6-1. Combining the 5-bit PWM together with the 3-bit BRM, the average duty cycle at the output will be (M+N/8)/32, where M is the content of the 5-bit PWM portion, and N is the content of the 3-bit BRM portion. Using this mechanism, a true 8-bit resolution PWM is achieved.
TPG
MC68HC05BD3
PULSE WIDTH MODULATION
MOTOROLA 6-1
The value of each PWM Data Register is continuously compared with the content of an internal counter to determine the state of each PWM channel output pin. Double buffering is not used in this PWM design.
32T=16s M=$00
T M=$01 31T
6
M=$0F
16T
16T
M=$1F
31T Pulse inserted at end of PWM cycle depends on setting of N.
T
T=1 CPU clock period (0.5s if CPU clock=2MHz) M = value set in 5-bit PWM (bit3-bit7) N = value set in 3-bit BRM (bit0-bit2)
N xx1 x1x 1xx
PWM cycles where pulses are inserted in a 8-cycle frame 4 2, 6 1, 3, 5, 7
Number of inserted pulses in a 8-cycle frame 1 2 4
Figure 6-1 8-Bit PWM Output Waveforms
TPG
MOTOROLA 6-2
PULSE WIDTH MODULATION
MC68HC05BD3
7
M-BUS SERIAL INTERFACE
M-Bus (Motorola Bus) is a two-wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices. It is fully compatible with the I2C bus standard. This two-wire bus minimizes the interconnection between devices and eliminates the need for address decoders; resulting in less PCB traces and economic hardware structure. This bus is suitable for applications requiring communications in a short distance among a number of devices. The maximum data rate is 100Kbit/s. The maximum communication length and number of devices that can be connected are limited by a maximum bus capacitance of 400pF. The M-Bus system is a true multi-master bus, including arbitration to prevent data collision if two or more masters intend to control the bus simultaneously. It may be used for rapid testing and alignment of end products via external connections to an assembly-line computer.
7
7.1
* * * * * * * * * *
M-Bus Interface Features
Compatible with I2C bus standard Multi-master operation 32 software programmable serial clock frequencies Software selectable acknowledge bit Interrupt driven byte-by-byte data transfer Arbitration lost driven interrupt with automatic mode switching from master to slave Calling address identification interrupt Generate/detect the start, stop and acknowledge signals Repeated START signal generation Bus busy detection
TPG
MC68HC05BD3
M-BUS SERIAL INTERFACE
MOTOROLA 7-1
Internal bus 8 Control register
MEN MIEN MSTA MTX TXAK
Status register
MCF MAAS MBB MAL SRW MIF RXAK
Frequency divider register
Address register
Interrupt
M-Bus interrupt Address comparator
SCL
SCL control
M-Bus clock generator sync logic TX shift register RX shift register
7
SDA SDA control
START, STOP detector and arbitration
START, STOP generator and timing sync
TX control
RX control
Figure 7-1 M-Bus Interface Block Diagram
7.2
M-Bus Protocol
Normally, a standard communication is composed of four parts, 1) START signal, 2) slave address transmission, 3) data transfer, and 4) STOP signal. They are described briefly in the following sections and illustrated in Figure 7-2.
TPG
MOTOROLA 7-2
M-BUS SERIAL INTERFACE
MC68HC05BD3
MSB SCL 1 1 0 0 0 0 1
LSB 1 Acknowledge bit
MSB 1 1 0 0 0 0 1
LSB 1 No acknowledge
SDA
START signal
STOP signal
MSB SCL 1 1 0 0 0 0 1
LSB 1 Acknowledge bit
MSB 1 1 0 0 0 0 1
LSB 1 No acknowledge
SDA
START signal
repeated START signal
STOP signal
7
Figure 7-2 M-Bus Transmission Signal Diagram
7.2.1
START Signal
When the bus is free, i.e., no master device is occupying the bus (both SCL and SDA lines are at logic high), a master may initiate communication by sending a START signal. As shown in Figure 7-2, a START signal is defined as a high to low transition of SDA while SCL is high. This signal denotes the beginning of a new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves.
7.2.2
Slave Address Transmission
The first byte of data transfer immediately following the START signal is the slave address transmitted by the master. This is a seven bits long calling address followed by a R/W bit. The R/W bit dictates the slave of the desired direction of data transfer. Only the slave with matched address will respond by sending back an acknowledge bit by pulling the SDA low at the 9th clock; see Figure 7-2.
TPG
MC68HC05BD3
M-BUS SERIAL INTERFACE
MOTOROLA 7-3
7.2.3
Data Transfer
Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in a direction specified by the R/W bit sent by the calling master. Each data byte is 8 bits long. Data can be changed only when SCL is low and must be held stable when SCL is high as shown in Figure 7-2. One clock pulse is for one bit of data transfer, MSB is transferred first. Each data byte has to be followed by an acknowledge bit. Hence, one complete data byte transfer requires 9 clock pulses. If the slave receiver does not acknowledge the master, the SDA line should be left high by the slave, the master can then generate a STOP signal to abort the data transfer or a START signal (repeated START) to commence a new calling. If the master receiver does not acknowledge the slave transmitter after one byte transmission, it means an "end of data" to the slave. The slave shall release the SDA line for the master to generate STOP or START signal.
7
7.2.4
Repeated START Signal
As shown in Figure 7-2, a repeated START signal is to generate a START signal without first generating a STOP signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.
7.2.5
STOP Signal
The master can terminate the communication by generating a STOP signal to free the bus. However, the master may generate a START signal followed by a calling command without generating a STOP signal first. This is called repeat START. A STOP signal is defined as a low to high transition of SDA while SCL is at a logical high; see Figure 7-2.
7.2.6
Arbitration Procedure
This interface circuit is a true multi-master system which allows more than one master to be connected. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock. The clock low period is equal to the longest clock low period among the masters; and the clock high period is the shortest among the masters. A data arbitration procedure determines the priority. A master will lose arbitration if it transmits a logic "1" while the others transmit logic "0", the losing master will immediately switch over to slave receive mode and stops its data and clock outputs. The transition from master to slave mode will not generate a STOP condition. Meanwhile, a software bit will be set by hardware to indicate loss of arbitration.
TPG
MOTOROLA 7-4
M-BUS SERIAL INTERFACE
MC68HC05BD3
7.2.7
Clock Synchronization
Since wire-AND logic is performed on the SCL line, a high to low transition on SCL line will affect the devices connected to the bus. The devices start counting their low period and once a device's clock has gone low, it will hold the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line, if another device clock is still in its low period. Therefore synchronized clock SCL will be held low by the device which releases SCL to a logic high in the last place. Devices with shorter low periods enter a high wait state during this time (see Figure 7-3). When all devices concerned have counted off their low period, the synchronized clock SCL line will be released and go high. All of them will start counting their high periods. The first device to complete its high period will again pull the SCL line low.
WAIT
Start counting high period
SCL1
SCL2
7
Internal counter reset
SCL
Figure 7-3 Clock Synchronization
7.2.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave device may hold the SCL low after completion of one byte transfer (9 bits). In such case, it will halt the bus clock and force the master clock in a wait state until the slave releases the SCL line.
7.3
M-Bus Registers
There are five registers used in the M-Bus interface, these are discussed in the following paragraphs.
TPG
MC68HC05BD3
M-BUS SERIAL INTERFACE
MOTOROLA 7-5
7.3.1
M-Bus Address Register (MADR)
Address $0017 bit 7 MAD7 bit 6 MAD6 bit 5 MAD5 bit 4 MAD4 bit 3 MAD3 bit 2 MAD2 bit 1 MAD1 bit 0 State on reset 0000 0000
MAD1-MAD7 are the slave address bits of the M-Bus module.
7.3.2
M-Bus Frequency Register (MFDR)
Address $0018 bit 7 bit 6 bit 5 bit 4 FD4 bit 3 FD3 bit 2 FD2 bit 1 FD1 bit 0 FD0 State on reset 0000 0000
FD0-FD4 are used for clock rate selection. The serial bit clock frequency is equal to the CPU clock divided by the divider shown in Table 7-1.
7
FD4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Table 7-1 M-Bus Prescaler
FD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DIVIDER 22 24 28 34 44 48 56 68 88 96 112 136 176 192 224 272 FD4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FD3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FD2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FD1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FD0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DIVIDER 352 384 448 544 704 768 896 1088 1408 1536 1792 2176 2816 3072 3584 4352
For a 4MHz external crystal operation (2MHz internal operating frequency), the serial bit clock frequency of M-Bus ranges from 460Hz to 90,909Hz.
TPG
MOTOROLA 7-6
M-BUS SERIAL INTERFACE
MC68HC05BD3
7.3.3
M-Bus Control Register (MCR)
Address $0019 bit 7 MEN bit 6 MIEN bit 5 MSTA bit 4 MTX bit 3 TXAK bit 2 bit 1 bit 0 State on reset 0000 0000
Register bit definitions: MEN - M-Bus Enable 1 (set) - M-Bus interface system enabled. M-Bus interface system disabled.
0 (clear) -
MIEN - M-Bus Interrupt Enable 1 (set) - M-Bus interrupt enabled. M-Bus interrupt disabled.
0 (clear) -
This bit enables the MIF (in MSR) for M-Bus interrupts. MSTA - Master/Slave Select 1 (set) - M-Bus is set for master mode operation. M-Bus is set for slave mode operation.
7
0 (clear) -
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a START signal is generated on the bus, and the master mode is selected. When this bit is changed from 1 to 0, a STOP signal is generated and the operation mode changes from master to slave. In master mode, a bit clear immediately followed by a bit set of this bit generates a repeated START signal without generating a STOP signal. MTX - Transmit/Receive Mode Select 1 (set) - M-Bus is set for transmit mode. M-Bus is set for receive mode.
0 (clear) -
TXAK - Acknowledge Enable 1 (set) - Do not send acknowledge signal. Send acknowledge signal at 9th clock bit.
0 (clear) -
If cleared, an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data. If set, no acknowledge signal response. This is an active low control bit.
TPG
MC68HC05BD3
M-BUS SERIAL INTERFACE
MOTOROLA 7-7
7.3.4
M-Bus Status Register (MSR)
Address $001A bit 7 MCF bit 6 MAAS bit 5 MBB bit 4 MAL bit 3 bit 2 SRW bit 1 MIF bit 0 RXAK State on reset 1000 0001
The MIF and MAL bits are software clearable; while the other bits are read only. MCF - Data Transfer Complete 1 (set) - A byte transfer has been completed. A byte is being transfer.
0 (clear) -
When MCF is set, the MIF (M-Bus interrupt) bit is also set. An M-Bus interrupt is generated if the MIEN bit is set. MAAS - Addressed as Slave 1 (set) - Currently addressed as a slave. Not currently addressed.
7
0 (clear) -
This MAAS bit is set when its own specific address (M-Bus Address register) matches the calling address. When MAAS is set, the MIF (M-Bus interrupt) bit is also set. An interrupt is generated if the MIEN bit is set. Then CPU needs to check the SRW bit and set its MTX bit accordingly. Writing to the M-Bus Control register clears this bit. MBB - Bus Busy 1 (set) - M-Bus busy. M-Bus idle.
0 (clear) -
This bit indicates the status of the bus. When a START signal is detected, MBB is set. When a STOP signal is detected, it is cleared. MAL - Arbitration Lost 1 (set) - Lost arbitration in master mode. No arbitration lost.
0 (clear) -
This arbitration lost flag is set when the M-Bus master loses arbitration during a master transmission mode. When MAL is set, the MIF (M-Bus interrupt) bit is also set. This bit must be cleared by software.
TPG
MOTOROLA 7-8
M-BUS SERIAL INTERFACE
MC68HC05BD3
SRW - Slave R/W Select 1 (set) - Read from slave, from calling master Write to slave from calling master.
0 (clear) -
When MAAS is set, the R/W command bit of the calling address sent from the master is latched into this SRW bit. By checking this bit, the CPU can then select slave transmit/receive mode by configuring MTX bit of the M-Bus Control register. MIF - M-Bus Interrupt 1 (set) - An M-Bus interrupt has occurred. An M-Bus interrupt has not occurred.
0 (clear) -
When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one of the following events occurs: 1) Completion of one byte of data transfer. It is set at the falling edge of the 9th clock - MCF set. 2) A match of the calling address with its own specific address in slave mode MAAS set. 3) A loss of bus arbitration - MAL set. This bit must be cleared by software in the interrupt routine. RXAK - Receive Acknowledge 1 (set) - No acknowledgment signal detected. Acknowledgment signal detected after 8 bits data transmitted.
7
0 (clear) -
If cleared, it indicates an acknowledge signal has been received after the completion of 8 bits data transmission on the bus. If set, no acknowledge signal has been detected at the 9th clock. This is an active low status flag.
7.3.5
M-Bus Data I/O Register (MDR)
Address $001B bit 7 MD7 bit 6 MD6 bit 5 MD5 bit 4 MD4 bit 3 MD3 bit 2 MD2 bit 1 MD1 bit 0 MD0 State on reset uuuu uuuu
In master transmit mode, data written into this register is sent to the bus automatically, with the most significant bit out first. In master receive mode, reading of this register initiates receiving of the next byte data. In slave mode, the same function applies after it has been addressed.
TPG
MC68HC05BD3
M-BUS SERIAL INTERFACE
MOTOROLA 7-9
Clear MIF
Y
Master Mode?
N
TX
TX/RX?
RX
N
Arbitration Lost? Y Clear MAL
Last byte transmitted? N
Y
Last byte to be read? N
Y
Generate STOP signal
MAAS=1? N
Y
7
RXAK=0? Y Write to MDR
N
Last 2nd byte to read? Y TXAK=1
N
MAAS=1? RX TX/RX? TX ACK from receiver? Y N Y Set RX mode Dummy read MDR Set TX mode Write to MDR Y N
N
SRW=1?
Generate STOP signal
Read from MDR
Write to MDR
RTI
Figure 7-4 Flowchart of M-Bus Interrupt Routine
TPG
MOTOROLA 7-10
M-BUS SERIAL INTERFACE
MC68HC05BD3
7.4 7.4.1
Programming Considerations Initialization
Reset will put the M-Bus Control register to its default status. Before the interface can be used to transfer serial data, the following initialization procedure must be carried out. 1) Update Frequency Divider Register (MFDR) to select an SCL frequency. 2) Update M-Bus Address Register (MADR) to define its own slave address. 3) Set MEN bit of M-Bus Control Register (MCR) to enable the M-Bus interface system. 4) Modify the bits of M-Bus Control Register (MCR) to select Master/Slave mode, Transmit/Receive mode, interrupt enable or not.
7.4.2
Generation of a START Signal and the First Byte of Data Transfer
After completion of the initialization procedure, serial data can be transmitted by selecting the master transmit mode. If the device is connected to a multi-master bus system, the state of the M-Bus busy bit (MBB) must be tested to check if the serial bus is free. If the bus is free (MBB=0), the START condition and the first byte (the slave address) can be sent. An example program which generates the START signal and transmits the first data byte (slave address) is shown below: CHFLAG SEI BRSET ; 5,MSR,CHFLAG ; ; ; 4,MCR ; 5,MCR ; ; #CALLING ; MDR ; ; ; DISABLE INTERRUPT CHECK THE MBB BIT OF THE STATUS REGISTER. IF IT IS SET, WAIT UNTIL IT IS CLEAR SET TRANSMIT MODE SET MASTER MODE i.e. GENERATE START CONDITION GET THE CALLING ADDRESS TRANSMIT THE CALLING ADDRESS ENABLE INTERRUPT
7
TXSTART
BSET BSET LDA STA CLI
7.4.3
Software Responses after Transmission or Reception of a Byte
Upon the completion of the transmission or reception of a data byte, the data transferring bit (MCF) will be set, indicating one byte communication has been finished. The M-Bus interrupt bit (MIF) will also be set to generate an M-Bus interrupt if the interrupt is enabled. Software must clear the
TPG
MC68HC05BD3
M-BUS SERIAL INTERFACE
MOTOROLA 7-11
MIF bit in the interrupt routine first. The MCF bit can be cleared by reading the M-Bus Data I/O Register (MDR) in receive mode or writing to the MDR in transmit mode. Software may serve the M-Bus I/O in the main program by monitoring the MIF bit if the interrupt is disabled. The following is an example of a software response by a master in transmit mode in the interrupt routine (see Figure 7-4). ISR BCLR BRCLR BRCLR BRSET ; ; ; 4,MCR,RECEIVE ; ; 0,MSR,END ; ; ; DATABUF ; MDR ; 1,MSR 5,MCR,SLAVE CLEAR THE MIF FLAG CHECK THE MSTA FLAG, BRANCH IF SLAVE MODE CHECK THE MODE FLAG, BRANCH IF IN RECEIVE MODE CHECK ACK FROM RECEIVER IF NO ACK, END OF TRANSMISSION GET THE NEXT BYTE OF DATA TRANSMIT THE DATA
TRANSMIT
LDA STA
7.4.4
Generation of the STOP Signal
7
A data transfer ends with a STOP signal generated by the master device. A master in transmit mode can simply generate a STOP signal after all the data have been transmitted. The following is an example showing how a STOP condition is generated by a master in transmit mode. MASTX BRSET 0,MSR,END LDA TXCNT BEQ LDA STA DEC BRA END BCLR EMASTX RTI END DATABUF MDR TXCNT EMASTX 5,MCR ; ; ; ; ; ; ; ; ; ; ; IF NO ACK, BRANCH TO END GET VALUE FROM THE TRANSMITTING COUNTER IF NO MORE DATA, BRANCH TO END GET NEXT BYTE OF DATA TRANSMIT THE DATA DECREASE THE TXCNT EXIT GENERATE A STOP CONDITION RETURN FROM INTERRUPT
If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data. This can be achieved by setting the transmit acknowledge bit (TXAK) before reading the 2nd last byte of data. Before reading the last byte of data, a STOP signal must be generated first. The following is an example showing how a STOP signal is generated by a master in receive mode. MASR DEC BEQ LDA DECA BNE RXCNT ENMASR RXCNT NXMAR ; LAST BYTE TO BE READ ; CHECK LAST 2ND BYTE TO BE READ ; NOT LAST ONE OR LAST SECOND
TPG
MOTOROLA 7-12
M-BUS SERIAL INTERFACE
MC68HC05BD3
LAMAR
BSET
3,MCR NXMAR 5,MCR MDR RXBUF
; LAST SECOND, DISABLE ACK ; TRANSMITTING ; LAST ONE, GENERATE 'STOP' ; SIGNAL ; READ DATA AND STORE
BRA ENMASR BCLR NXMAR LDA STA RTI
7.4.5
Generation of a Repeated START Signal
At the end of data transfer, if the master still wants to communicate on the bus, it can generate another START signal followed by another slave address without first generating a STOP signal. A program example is as shown. RESTART BCLR BSET LDA STA 5,MCR 5,MCR #CALLING MDR ; ; ; ; ; ; ANOTHER START (RESTART) IS GENERATED BY THESE TWO CONSECUTIVE INSTRUCTIONS GET THE CALLING ADDRESS TRANSMIT THE CALLING ADDRESS
7
7.4.6
Slave Mode
In the slave service routine, the master addressed as slave bit (MAAS) should be tested to check if a calling of its own address has been received (Figure 7-4). If MAAS is set, software should set the transmit/receive mode select bit (MTX bit of MCR) according to the R/W command bit (SRW). Writing to the MCR clears the MAAS automatically. A data transfer may then be initiated by writing to MDR or a dummy read from MDR. In the slave transmit routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. RXAK, if set indicates the end of data signal from the master receiver, the slave transmitter must then switch from transmit mode to receive mode by software and a dummy read must follow to release the SCL line so that the master can generate a STOP signal.
7.4.7
Arbitration Lost
If more than one master want to acquire the bus simultaneously, only one master can win and the others will lose arbitration. The losing device immediately switches to slave receive mode by M-Bus hardware. Its data output to the SDA line is stopped, but internal transmit clock still runs until the end of the data byte transmission. An interrupt occurs when this dummy byte transmission
TPG
MC68HC05BD3
M-BUS SERIAL INTERFACE
MOTOROLA 7-13
is accomplished with MAL=1 and MSTA=0. If one master attempts to start transmission while the bus is being controlled by another master, the transmission will be inhibited; the MSTA bit will be changed from 1 to 0 without generating STOP condition; an interrupt will be generated and the MAL bit set to indicate that the attempt to acquire the bus has failed. Considering these cases, the slave service routine should test the MAL bit first, and software should clear the MAL bit if it is set.
7
TPG
MOTOROLA 7-14
M-BUS SERIAL INTERFACE
MC68HC05BD3
8
SYNC SIGNAL PROCESSOR
The functions of the SSP include polarity correction, sync separation, sync pulse reshaper, sync pulse detectors, horizontal line counter, vertical frequency counter, and free running signals generator. In addition, interrupt can be generated for each vertical frame at a user specified horizontal line number. The processor accepts either composite or separate sync inputs. For separate sync inputs, the HTTL and VTTL outputs are identical to the incoming horizontal sync with negative sync polarity. As for composite sync input, reassembled horizontal sync pulses can be inserted during the vertical sync period. The VTTL output is triggered by the leading edge of the incoming vertical sync pulse, and the sync pulse will be widened by 9.5s. Both HSYNC and VSYNC inputs have internal filter to improve noise immunity. Any pulse that is shorter than an internal bus clock period, will be regarded as a glitch, and will be ignored.
8
Note:
All quoted timings in this section are based on the assumption that the internal bus frequency is 2MHz, i.e. tCYC =0.5s.
8.1
Functional Blocks
The architecture of the Sync Signal Processor is shown in Figure 8-1. Each of the functional blocks are described in the following paragraphs.
8.1.1
Polarity Correction
The polarity correction block of the sync signal processor accepts the input sync signals (HSYNC/VSYNC) and converts them to negative polarity signals, regardless of the polarity of the inputs. The following describes the methodologies used in polarity correction.
TPG
MC68HC05BD3
SYNC SIGNAL PROCESSOR
MOTOROLA 8-1
VSIN
FOUT
V FREQ. REGISTER
$0D $0E
VSYNC COUNTER VSYNC POLARITY CORRECTOR MUX COMPOSITE POLARITY CORRECTOR CLK GEN. HFREE SYNC SEPARATOR & INSERTION V VSYNC RESHAPER VFREE
SYNC DETECTOR
VDET
MUX R S R MUX
VTTL
HSYNC
SOUT
HTTL
H
8
$11
SYNC SIGNAL CONTROL REG.
INTERRUPT CIRCUIT
HSYNC COUNTER
SYNC DETECTOR
HDET
INTERRUPT
LINE FREQ. REGISTERS
$0F $10
Figure 8-1 Sync Signal Processor Block Diagram
8.1.1.1
Separate Vertical Sync Input
To test the polarity of the input sync signal, the duration of the low pulse is examined. If the low period is longer than a specific value (512s or 1024tCYC), as in the case of positive polarity input sync, the input sync will be inverted before output. For negative polarity input sync signal, it is anticipated that the duration of the low pulse would be shorter than the specific value, and the input sync signal passes through to the output without inversion. This polarity correction is a continuous process, and the error margin is equal to the maximum permissible sync pulse width specified (512s or 1024tCYC). At power-up or system reset, negative polarity at input is assumed.
TPG
MOTOROLA 8-2
SYNC SIGNAL PROCESSOR
MC68HC05BD3
Positive polarity pure horizontal sync signal
Negative polarity pure horizontal sync signal
Positive polarity composite sync signal
Negative polarity composite sync signal
Figure 8-2 Sync Signal Polarity Correction
8.1.1.2
Separate Horizontal Or Composite Sync Input
Since the input at HSYNC can be either a pure horizontal sync signal or a composite sync signal, different methodologies are used in polarity correction. Unlike the polarity correction for VSYNC, both the high pulse and low pulse of the sync signal at HSYNC are examined. If the pulse, either active high or low, is longer than a certain period (8s or 16 tCYC), it will be regarded as a long pulse. If there are 8 consecutive low long pulses, the input sync signal will be confirmed as a positive polarity sync signal, and will be inverted. If there are 8 consecutive high long pulses, it will be confirmed as a negative polarity sync signal. The operation of this module is also continuous, and the error margin is equal to the period of the pre-set number (default is 8) of horizontal sync pulses. At power-up or system reset, negative polarity at input is assumed.
8
8.1.2
Sync Detection
The sync detector determines whether the incoming sync signal is active. Both sync high and low pulse widths must be within the specific values to be regarded as active. HDET and VDET flags will be set if the HSYNC and VSYNC signals are active, respectively.
TPG
MC68HC05BD3
SYNC SIGNAL PROCESSOR
MOTOROLA 8-3
8.1.3
Free-running Pseudo Sync Signal Generator
If either HSYNC or VSYNC is absent, a free-running sync signal generator will be enabled. It generates a pseudo vertical sync at 63.5Hz (1/(tcyc x 31488)) and a pseudo horizontal sync at either 48.8KHz (1/(tCYC x 41)) or 62.5KHz (1/(tCYC x 32)), depending on the status of FOUT. This set of free running sync signals replaces the inactive sync signals at the inputs and will be fed to the VTTL and HTTL pins if the pins are selected for VTTL and HTTL function.
8.1.4
Sync Separation
Figure 8-3 is a block diagram of the Sync Separator which includes the duration counters for the high and low pulses, a counter for the number of valid horizontal sync pulses, a register to hold the number of horizontal lines per frame, a logic block for horizontal and vertical sync pulse separation, a comparator, and a sync pulse insertion circuit.
CLK
HSYNC (After polarity correction)
load Horizontal Sync Register Horizontal sync pulse counter in out
8
Low pulse duration counter High pulse duration counter finish
reset
count
Comparator equal
Sync separation logic
Sync insertion circuit
Hsync
Vsync
Figure 8-3 Sync Separator
The Low pulse duration counter examines the low pulse width of the incoming composite sync signal. If it is within the horizontal sync pulse limit (8s or 16 tCYC), a horizontal sync pulse is detected and the horizontal sync pulse counter is advanced. If the low pulse is wider than the limit,
TPG
MOTOROLA 8-4
SYNC SIGNAL PROCESSOR
MC68HC05BD3
a vertical sync pulse is detected, and the content of the Horizontal sync pulse counter is loaded into the Horizontal Sync Register before the Low Pulse Duration Counter is reset. Comparator compares the values of the Horizontal Sync Pulse Counter and Horizontal Sync Register, and gives the equal signal to the Sync Separation Logic. High Pulse Duration Counter examines the high pulse width of the incoming composite sync signal. If it is longer than a specific value (8s or 16 tCYC), the vertical sync pulse has finished and finish signal will be given to the Sync Separation Logic. Sync Separation Logic passes the composite sync signal to the Hsync output, until there is an "equal" signal from the comparator. The Hsync output will then output a reassembled waveform by the Sync Insertion Circuit to emulate the HSYNC pulses, and the Vsync output is set to low at the coming falling edge of the composite signal. After the finish signal has been sensed, the Vsync output is fixed to high, and the Hsync output follows the composite sync input again.
8.1.5
Vertical Sync Pulse Reshaper
For separate sync inputs, the vertical sync pulse width VTTL equals to the incoming vertical sync input. For composite sync input, the Sync Pulse Reshaper widens the VTTL pulse width by 9.5s.
8.1.6
Sync Signal Counters
8
There are two counters (horizontal line counter and vertical frequency counter) to count the number of horizontal sync pulses and the number of system clock cycles between two vertical sync pulses. These two data can be read by the CPU to check the signal frequencies and can be used to determine the video mode. Figure 8-4 shows a more detailed block diagram of these counters. The 13-bit vertical frequency register encompasses vertical frequency range from approximately 15Hz to 125KHz. Figure 8-5 shows the vertical frequency counter timing. It indicates that there will be 1 count error on the reading from the register for the same vertical frequency.
8.2
VSYNC Interrupt
The Sync Signal Processor will generate interrupts to the CPU if the VSYNC Interrupt Enable (VSIE) bit is set, and the I-bit in the Condition Code Register (CCR) is cleared. The interrupt will occur at each leading edge of VSYNC. The interrupt vector address is at $3FF8-$3FF9, and the interrupt latch is cleared automatically by fetching of the interrupt vectors.
TPG
MC68HC05BD3
SYNC SIGNAL PROCESSOR
MOTOROLA 8-5
$0D $0E
13-bit Vertical Frequency Register
System Clock
/16
13-bit counter R
VSYNC
Negative edge detector R
HSYNC
Negative edge detector
12-bit counter
$0F $10
12-bit Horizontal Line Count Register
Figure 8-4 Sync Signal Counters Block Diagram
8
PH2 VSYNIN Counter signal reset PH2 /16 case1 PH2 /16 case2 Counter advances at the rising edge of the clock 1. The value of the counter will be loaded into the register before it is reset. 2. The Vertical Frequency Counter is clocked by a PH2 /16 clock. 3. Because of the asynchronous nature between PH2 and VSYNIN, the register will have one more count in case 2 than in case 1. Counter resets at 4 PH2 cycles after falling edge of VSYNIN
Figure 8-5 Vertical Frequency Counter Timing
TPG
MOTOROLA 8-6
SYNC SIGNAL PROCESSOR
MC68HC05BD3
8.3
Registers
There are seven registers associated with the Sync Signal Processor, these are described below.
8.3.1
Sync Signal Control & Status Register (SSCSR)
Address $000C bit 7 VPOL bit 6 HPOL bit 5 VDET bit 4 HDET bit 3 SOUT bit 2 INSRTB bit 1 FOUT bit 0 VSIN State on reset 0000 0000
VPOL - Vertical Sync Input Polarity 1 (set) - VSYNC input is positive polarity. VSYNC input is negative polarity.
0 (clear) -
Vertical Sync Input Polarity flag indicates the polarity of the incoming signal at the VSYNC input. HPOL - Horizontal Sync Input Polarity 1 (set) - HSYNC input is positive polarity. HSYNC input is negative polarity.
0 (clear) -
Horizontal Sync Input Polarity flag indicates the polarity of the incoming signal at the HSYNC input. VDET - Vertical Sync Signal Detect 1 (set) - An active vertical sync is detected at VSYNC input. No vertical sync signal at VSYNC input; use internal generated Vsync for VTTL.
8
0 (clear) -
Vertical Sync Signal Detect flag, if set, indicates an active input vertical sync signal has been detected. If cleared, it indicates there is no active signal, and the VTTL will output the internally generated Vsync signal. An active vertical sync signal is defined as:
VDET = (VSYNC pulse width < 480s or 960tCYC)*(VSYNC period < 65.5ms or 131x103tCYC)
HDET - Horizontal Sync Signal Detect 1 (set) - An active horizontal sync is detected at HSYNC input. No horizontal sync signal at HSYNC input; use internal generated Hsync for HTTL.
0 (clear) -
Horizontal Sync Signal Detect flag, if set, indicates an active input horizontal sync signal has been detected. If cleared, it indicates there is no active signal, and the HTTL will output the internally generated Hsync signal. An active horizontal sync signal is defined as:
HDET=(HSYNC pulse width < 8s or 16tCYC)*(9s or 18tCYC < HSYNC period < 128s or 256tCYC)
TPG
MC68HC05BD3
SYNC SIGNAL PROCESSOR
MOTOROLA 8-7
SOUT - Sync Output Select 1 (set) - Use processed VSYNC and HSYNC inputs for VTTL and HTTL. Use internally generated sync signals for VTTL and HTTL.
0 (clear) -
When cleared, the outputs to VTTL and HTTL are the internally generated signals. When set, the outputs are the processed input signals. This bit can only be set if both VDET and HDET are logic 1's, and will be cleared automatically if VDET or HDET is not logic "1". Reset clears this bit. INSRTB - Hsync Insertion Bit 1 (set) - No inserted pulses. Hsync remains high state during the vertical sync pulse. For composite sync inputs, emulated sync pulses will be inserted into the Hsync signal during the vertical sync pulse.
0 (clear) -
For separate sync inputs, when this Hsync Insertion bit is cleared, sync pulses will continue to be the Hsync signal during the Vertical Sync Pulse. For composite sync input, when this Hsync Insertion bit is cleared, emulated sync pulses will be inserted into the Hsync signal during the Vertical Sync Pulse. In both cases, when this bit is set, there will be no inserted pulses, and the Hsync signal will be high during the Vertical Sync Pulse. Reset clears this bit. FOUT - Internal Hsync Frequency Select
8
1 (set)
-
63.5Hz and 62.5KHz for VTTL and HTTL outputs respectively if internally generated sync signals are selected. 63.5Hz and 48.8KHz for VTTL and HTTL outputs respectively if internally generated sync signals are selected.
0 (clear) -
This bit selects the frequency of the free running Hsync signal to HTTL pin if SOUT bit is cleared. When FOUT is set, 63.5Hz and 62.5KHz signals are output to VTTL and HTTL, respectively. When FOUT is cleared, 63.5Hz and 48.8KHz signals are output instead. Reset clears this bits. VSIN - Vsync Input Source This bit selects the source of the input sync signals. Reset clears this bits. 1 (set) - Separated sync signals through VSYNC and HSYNC inputs. Composite sync signal through HSYNC input
0 (clear) -
TPG
MOTOROLA 8-8
SYNC SIGNAL PROCESSOR
MC68HC05BD3
8.3.2
Vertical Frequency Registers (VFRS)
Address bit 7 VFHR VFLR $000D $000E VF7 VF6 VF5 bit 6 bit 5 bit 4 VF12 VF4 bit 3 VF11 VF3 bit 2 VF10 VF2 bit 1 VF9 VF1 bit 0 VF8 VF0 State on reset 0000 0000 0000 0000
This 13-bit read only register pair contains information of the vertical frame frequency. An internal counter counts the number of internal clocks between two VSYNC pulses. The counted value will then be transferred to this register. The data corresponds to the period of one vertical frame. This register can be read to determine if the frame frequency is valid, and to determine the video mode. However, the data is not valid if VDET bit is cleared. The frame frequency is calculated by 1/(VFR1 x 8s) or 1/(VFR1 x 16tCYC). The table below shows examples for the Vertical Frequency Register, all VFR numbers are in hexadecimal.
Table 8-1 Vertical Frame Frequencies
VFR $03C0 $03C1 $03C2 $04E2 $04E3 $04E4 $06F9 $06FA $06FB Min. Freq. 130.07 129.94 129.80 99.92 99.84 99.76 69.99 69.95 69.91 Max. Freq. 130.34 130.21 130.07 100.08 100.00 99.92 70.07 70.03 69.99 VFR $0823 $0824 $0825 $09C4 $09C5 $09C6 $1FFD $1FFE $1FFF Min. Freq. 59.98 59.95 59.92 49.98 49.96 49.94 15.262 15.260 15.258 Max. Freq. 60.04 60.01 59.98 50.02 50.00 49.98 15.266 15.264 15.262
8
8.3.3
Line Frequency Registers (LFRs)
Address bit 7 LFHR LFLR $000F HOVER $0010 LF7 LF6 LF5 LF4 bit 6 bit 5 bit 4 bit 3 LF11 LF3 bit 2 LF10 LF2 bit 1 LF9 LF1 bit 0 LF8 LF0 State on reset 0000 0000 0000 0000
This 12-bit read only register pair contains the number of horizontal lines in each vertical frame. An internal line counter counts the horizontal sync pulses between two vertical sync pulses. The counted value will be transferred to this register pair. HOVER bit will be set if the incoming horizontal sync pulses between two vertical sync pulses are more than 4096 or there is no vertical
TPG
MC68HC05BD3
SYNC SIGNAL PROCESSOR
MOTOROLA 8-9
sync input. The data can be read to determine if the line frequency is valid and to determine the video mode. However, the data is not valid if HDET or VDET bit is cleared or HOVER bit is set. User has to determine whether the incoming signal is separate sync or composite sync. If composite sync signal is input, the actual number of horizontal lines is the value in LFR plus one; because the internal line counter that counts the horizontal sync pulses is rising-edge triggering. If the incoming signal is a composite signal, one horizontal line counting is missed.
8.3.4
Sync Signal Control Register (SSCR)
Address $0011 bit 7 VSIE bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000
This is a read/write register. Interrupt will be generated at the leading edge of VSYNC if the VSIE bit is set, I bit in CCR is cleared. The VSYNC interrupt vectors are at $3FF8 and $3FF9, and the interrupt latch is cleared after the interrupt vectors have been fetched. VSIE - Vsync Interrupt Enable This bit enables and disables the Vsync interrupt.
8
8.3.5
1 (set)
-
Vsync interrupt enabled. Vsync interrupt disabled.
0 (clear) -
Horizontal Sync Period Width Register (HPWR)
Address $001E bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 State on reset 0000 0000
HPWR7 HPWR6 HPWR5 HPWR4 HPWR3 HPWR2 HPWR1 HPWR0
This 8-bit read only register contains the period of incoming horizontal sync signal. It is sampled by tCYC so the horizontal period is equal to HPWR x 0.5s if tCYC is at 2MHz. As the incoming horizontal sync signal is asynchronous to the system clock, the SSP is designed so that the maximum counting error of HPWR is -2. User should use the LFR to calculate the HSYNC frequency if very accurate frequency detection is needed. If HPWR overflows, the HDET in SSCSR will be cleared. Therefore the minimum valid HSYNC is 256tCYC, i.e. 7.8125KHz if tCYC equals to 2MHz.
Note:
It is not guaranteed that the HPWR counting is correct for the first HSYNC period after the trailing edge of VSYNC.
TPG
MOTOROLA 8-10
SYNC SIGNAL PROCESSOR
MC68HC05BD3
8.4
System Operation
The incoming signals can be either separate HSYNC and VSYNC or composite sync through HSYNC input. Polarity correction is performed before the sync signals go any further into the system. The sync pulse detection block continuously monitors the signals to see if the signals are active. If the signals are not active, the circuit switches to output the internally generated sync signals. This will protect the circuits behind from being damaged by inactive signals. A typical monitor system operation is summarized in Figure 8-6.
Note:
User is required to check the HDET and VDET at VSIN=0 first. If either or both are not detected, user then set VSIN=1 to check HDET and VDET. It is because if the incoming signal is a valid composite signal, HDET and VDET are both read 1 even VSIN=1. Each time if VDET is not detected when VSIN=1, user needs to clear VSIN to check VDET. If VDET is still not detected, user then set VSIN to check them again to decide what mode it is.
Note:
8
TPG
MC68HC05BD3
SYNC SIGNAL PROCESSOR
MOTOROLA 8-11
Clear 1st_time Init VSIN=0
A
B
VDET=0? N Y
Y
Set VSIN=1
HDET=1? N
VDET=0? N Y
Y
Y
HOVER=1? Set VSIN=1 N B
HDET=1? N
HSYNC too high No HSYNC signal Set Standby mode Y
8
VDET=0? Set SOUT=1 N Y Read registers
Y
1st_time=0? N
HDET=1? N Y
Set 1st_time=1
HDET=1? N
VSIN=1? N Separated sync Set Normal mode
Y
No HSYNC Set Standby mode Clear VSIN=0
Clear VSIN=0
No VSYNC Set Suspend mode Composite sync Set Normal mode
No VSYNC No HSYNC Set Off mode
A
Figure 8-6 Typical Monitor System Operation
TPG
MOTOROLA 8-12
SYNC SIGNAL PROCESSOR
MC68HC05BD3
9
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the addressing modes of the MC68HC05BD3.
9.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 9-1. The interrupt stacking order is shown in Figure 9-2.
7 7 15 7 00 15 7 0000000011 7 111HINZ 0 Accumulator 0 Index register 0 Program counter 0 Stack pointer 0 C Condition code register Carry / borrow Zero Negative Interrupt mask Half carry
9
Figure 9-1 Programming model
9.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations.
TPG
MC68HC05BD3
CPU CORE AND INSTRUCTION SET
MOTOROLA 9-1
7 Increasing memory address Condition code register Accumulator Index register Program counter high Program counter low Return
0
Stack Interrupt Decreasing memory address
Unstack
Figure 9-2 Stacking order
9.1.2
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area.
9.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
9.1.4
Stack pointer (SP)
9
The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. These ten bits are appended to the six least significant register bits to produce an address within the range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
9.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. Half carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
TPG
MOTOROLA 9-2
CPU CORE AND INSTRUCTION SET
MC68HC05BD3
Interrupt (I) When this bit is set, all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during bit test and branch instructions and during shifts and rotates.
9.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as follows: - - - - - Register/memory Read/modify/write Branch Bit manipulation Control
9
The following paragraphs briefly explain each type. All the instructions within a given type are presented in individual tables. This MCU uses all the instructions available in the M146805 CMOS family plus one more: the unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is then stored in the index register and the low-order product is stored in the accumulator. A detailed definition of the MUL instruction is shown in Table 9-1.
TPG
MC68HC05BD3
CPU CORE AND INSTRUCTION SET
MOTOROLA 9-3
9.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Refer to Table 9-2 for a complete list of register/memory instructions.
9.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. Refer to Table 9-3.
9.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space (page 0). All port data and data direction registers, timer and serial interface registers, control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. Refer to Table 9-4.
9
9.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. Refer to Table 9-5 for a complete list of read/modify/write instructions.
9.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation during program execution. Refer to Table 9-6 for a complete list of control instructions.
9.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical listing of all the instructions (see Table 9-7), and an opcode map for the instruction set of the M68HC05 MCU family (see Table 9-8).
TPG
MOTOROLA 9-4
CPU CORE AND INSTRUCTION SET
MC68HC05BD3
Table 9-1 MUL instruction
X:A X*A Multiplies the eight bits in the index register by the eight Description bits in the accumulator and places the 16-bit result in the concatenated accumulator and index register. H : Cleared I : Not affected Condition N : Not affected codes Z : Not affected C : Cleared Source MUL Addressing mode Cycles Bytes Opcode Form Inherent 11 1 $42 Operation
Table 9-2 Register/memory instructions
Addressing modes Immediate Mnemonic Direct Extended Indexed (no offset) # Cycles Opcode Opcode # Bytes Indexed (8-bit offset) # Cycles Opcode # Bytes Indexed (16-bit offset) # Cycles 5 5 6 6 5 5 5 5 5 5 5 5 5 5 4 7 # Bytes 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
# Cycles
# Cycles
Function Load A from memory Load X from memory Store A in memory Store X in memory Add memory to A Add memory and carry to A Subtract memory Subtract memory from A with borrow AND memory with A OR memory with A Exclusive OR memory with A Arithmetic compare A with memory Arithmetic compare X with memory Bit test memory with A (logical compare) Jump unconditional Jump to subroutine
LDA LDX STA STX ADD ADC SUB SBC AND ORA EOR CMP CPX BIT JMP JSR
A6 AE
2 2
2 2
B6 BE B7 BF
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5
C6 CE C7 CF CB C9 C0 C2 C4 CA C8 C1 C3 C5 CC CD
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
# Cycles 4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6
Opcode
Opcode
Opcode
# Bytes
# Bytes
# Bytes
F6 FE F7 FF FB F9 F0 F2 F4 FA F8 F1 F3 F5 FC FD
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3 3 4 4 3 3 3 3 3 3 3 3 3 3 2 5
E6 EE E7 EF EB E9 E0 E2 E4 EA E8 E1 E3 E5 EC ED
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
4 4 5 5 4 4 4 4 4 4 4 4 4 4 3 6
D6 DE D7 DF DB D9 D0 D2 D4 DA D8 D1 D3 D5 DC DD
9
AB A9 A0 A2 A4 AA A8 A1 A3 A5
2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2
BB B9 B0 B2 B4 BA B8 B1 B3 B5 BC BD
TPG
MC68HC05BD3
CPU CORE AND INSTRUCTION SET
MOTOROLA 9-5
Table 9-3 Branch instructions
Relative addressing mode Opcode # Bytes # Cycles 20 2 3 21 2 3 22 2 3 23 2 3 24 2 3 24 2 3 25 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 2A 2 3 2B 2 3 2C 2 3 2D 2 3 2E 2 3 2F 2 3 AD 2 6
Function Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear (Branch if higher or same) Branch if carry set (Branch if lower) Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit is clear Branch if interrupt mask bit is set Branch if interrupt line is low Branch if interrupt line is high Branch to subroutine
Mnemonic BRA BRN BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR
9
Function Branch if bit n is set Branch if bit n is clear Set bit n Clear bit n
Table 9-4 Bit manipulation instructions
Addressing modes Bit set/clear Bit test and branch Opcode # Bytes # Cycles Opcode # Bytes # Cycles 2*n 3 5 01+2*n 3 5 10+2*n 2 5 11+2*n 2 5
Mnemonic BRSET n (n=0-7) BRCLR n (n=0-7) BSET n (n=0-7) BCLR n (n=0-7)
TPG
MOTOROLA 9-6
CPU CORE AND INSTRUCTION SET
MC68HC05BD3
Table 9-5 Read/modify/write instructions
Addressing modes Inherent (A) Mnemonic # Cycles Opcode Inherent (X) # Cycles Opcode Opcode Direct Indexed (no offset) # Cycles # Cycles Opcode # Bytes Indexed (8-bit offset) # Cycles 6 6 6 6 6 6 6 6 6 6 5 Opcode 6C 6A 6F 63 60 69 66 68 64 67 6D # Bytes 2 2 2 2 2 2 2 2 2 2 2
# Bytes
# Bytes
Function Increment Decrement Clear Complement Negate (two's complement) Rotate left through carry Rotate right through carry Logical shift left Logical shift right Arithmetic shift right Test for negative or zero Multiply
INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST MUL
4C 4A 4F 43 40 49 46 48 44 47 4D 42
1 1 1 1 1 1 1 1 1 1 1 1
3 5C 3 5A 3 5F 3 53 3 50 3 59 3 56 3 58 3 54 3 57 3 5D 11
1 1 1 1 1 1 1 1 1 1 1
3 3 3 3 3 3 3 3 3 3 3
3C 3A 3F 33 30 39 36 38 34 37 3D
# Bytes 2 2 2 2 2 2 2 2 2 2 2
5 5 5 5 5 5 5 5 5 5 4
7C 7A 7F 73 70 79 76 78 74 77 7D
1 1 1 1 1 1 1 1 1 1 1
5 5 5 5 5 5 5 5 5 5 4
Table 9-6 Control instructions
Inherent addressing mode Opcode # Bytes # Cycles 97 1 2 9F 1 2 99 1 2 98 1 2 9B 1 2 9A 1 2 83 1 10 81 1 6 80 1 9 9C 1 2 9D 1 2 8E 1 2 8F 1 2
Function Transfer A to X Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-operation Stop Wait
Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT
9
TPG
MC68HC05BD3
CPU CORE AND INSTRUCTION SET
MOTOROLA 9-7
Table 9-7 Instruction set
Addressing modes EXT REL IX IX1 Condition codes I NZ * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * 0 * * * 01 *
Mnemonic ADC ADD AND ASL ASR BCC BCLR BCS BEQ BHCC BHCS BHI BHS BIH BIL BIT BLO BLS BMC BMI BMS BNE BPL BRA BRN BRCLR BRSET BSET BSR CLC CLI CLR CMP
INH
IMM
DIR
IX2
BSC BTB
9
H * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
C * * * * * * * * * * * * * * * * * * * * * * * 0 * *
Address mode abbreviations
BSC Bit set/clear BTB DIR EXT INH Bit test & branch Direct Extended Inherent IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative I N Z C Not implemented H
Condition code symbols
Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set
TPG
MOTOROLA 9-8
CPU CORE AND INSTRUCTION SET
MC68HC05BD3
Table 9-7 Instruction set (Continued)
Addressing modes EXT REL IX IX1 Condition codes I NZ * * * * * * * * * * * * * * * 0 * * * * * * * * * * * * * ??? * * * * * * * 1 * * * 0 * * * * 1 * * * * * * * * * 0 * *
Mnemonic COM CPX DEC EOR INC JMP JSR LDA LDX LSL LSR MUL NEG NOP ORA ROL ROR RSP RTI RTS SBC SEC SEI STA STOP STX SUB SWI TAX TST TXA WAIT
INH
IMM
DIR
IX2
BSC BTB
H * * * * * * * * * * * 0 * * * * * * ? * * * * * * * * * * * * *
C 1 * * * * * * * 0 * * * ? * 1 * * * * * * * * *
9
Address mode abbreviations
BSC Bit set/clear BTB DIR EXT INH Bit test & branch Direct Extended Inherent IMM IX IX1 IX2 REL Immediate Indexed (no offset) Indexed, 1 byte offset Indexed, 2 byte offset Relative I N Z C Not implemented H
Condition code symbols
Half carry (from bit 3) Interrupt mask Negate (sign bit) Zero Carry/borrow * ? 0 1 Tested and set if true, cleared otherwise Not affected Load CCR from stack Cleared Set
TPG
MC68HC05BD3
CPU CORE AND INSTRUCTION SET
MOTOROLA 9-9
9
Control High
3 IX 3
MOTOROLA 9-10
DIR 3 0011
3
High NEG
DIR 1 INH 1 INH 2 IX1 1 IX 1 5
Low NEGA RTS
1 INH 2 INH 6 2 3
Bit manipulation BTB BSC 0 1 0000 0001 INH 4 0100 NEGX CMP SBC
2 IMM 2 2 IMM 2 2 3
Branch REL 2 0010 IX 7 0111
6
Read/modify/write INH IX1 5 6 0101 0110 INH 8 1000
5
INH 9 1001
9
IMM A 1010 SUB CMP SBC CPX AND BIT LDA STA
2 DIR 3 4 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 2
DIR B 1011 SUB CMP SBC CPX AND BIT LDA STA EOR ADC
DIR 3 3 DIR 3 3 EXT 3 5 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 EXT 3 4 3
Register/memory EXT IX2 C D 1100 1101 IX1 E 1110
5
IX F 1111
4
BRSET0
REL 2 3
5
BSET0 CMP SBC CPX AND BIT LDA STA
EXT 3 4 EXT 3 4 EXT 3 4 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5
5
BRA CMP SBC CPX AND BIT
IX2 2 5 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4
NEG CMP SBC CPX AND BIT LDA
IX2 2 6 IX1 1 4
NEG
RTI
SUB
4
SUB
SUB
SUB
3
BRCLR0
REL 3
BTB 2 5
BCLR0 MUL
1 11 REL 3
BSC 2 5 IX 3
BRN
3
BRSET1 COM LSR
DIR 1 INH 1 INH 2 IX1 1 IX 2 DIR 1 5 5
BTB 2 5 INH 3
BSET1 COMA LSRA BIT
2 IMM 2 2 INH 1 3
BSC 2 5
BHI COMX LSRX
INH 2 3 3
3
BRCLR1
REL 2 3
BTB 2 5
BCLR1 LSR
IX1 1 6
BSC 2 5
BLS LSR
IX 1 5 INH 2
COM AND
IMM 2 2
6
COM
5
SWI
10
CPX
IMM 2 2
IX 3 IX 3 IX 3
3
BRSET2
REL 2 3 REL 3
BTB 2 5
BSET2
BSC 2 5
BCC
3
BRCLR2 ROR ASR LSL ROL DEC
DIR 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 5 DIR 1 5 DIR 1 5 DIR 1 5 5
BTB 2 5
BCLR2 RORA ASRA LSLA ROLA DECA SEI
1 INH 2 2 INH 1 3 INH 1 3 INH 1 3 INH 1 3 3
BSC 2 5
BCS RORX ASRX LSLX ROLX DECX ADD
IMM 2 2 IMM 2 INH 2 3 INH 2 3 INH 2 3 INH 2 3 3
3
BRSET3
REL 2 3
BTB 2 5
BSET3 ASR LSL ROL DEC
IX1 1 6 IX1 1 6 IX1 1 6 IX1 1 6
BSC 2 5
BNE ASR LSL ROL DEC
IX 5 1 IX 5 1 IX 5 1 IX 5 2 IMM 2
ROR TAX CLC SEC CLI
INH 2 2 INH 2 2 INH 2 2
6
ROR
5
LDA
IMM 2 2
LDA STA EOR ADC
IX2 2 5 IX2 2 5 IX2 2 5 IX1 1 5
IX 3 IX 4
3
BRCLR3
REL 2 3
BTB 2 5
BCLR3 EOR ADC ORA
IMM 2 2 IMM 2 2 2
BSC 2 5 DIR 3 3 DIR 3 3
BEQ EOR ADC ORA ADD JMP
2 REL 2 3
STA EOR ADC
IX1 1 4 IX1 1 4 IX1 1 4
3
BRSET4
REL 2 3 REL 2 3 REL 3
BTB 2 5
BSET4
BSC 2 5
BHCC
EOR ADC ORA ADD ORA
EXT 3 4
IX 3 IX 3 IX 3
3
BRCLR4
BTB 2 5
BCLR4
BSC 2 5
BHCS
3
BRSET5
BTB 2 5
BSET5
BSC 2 5
BPL
ORA ADD
DIR 3 2 IX2 2 5
ORA ADD JMP
EXT 3 3 IX1 1 4
3
BRCLR5 INC TST
DIR 1 INH 1 INH 2 IX1 1 IX 1 DIR 1 4 5
BTB 2 5
BCLR5 INCA TSTA STOP
1 2 2 INH 1 3 3
BSC 2 5
BMI INCX TSTX
INH 2 3 3
ADD JMP
IX2 2 4
IX 3
3
BRSET6
REL 2 3
BTB 2 5
BSET6 TST
IX1 1 5
BSC 2 5
BMC TST
IX 4 1
INC NOP
INH 2 INH 2
6
INC
5
RSP
INH 2 2
JMP BSR LDX
6 REL 2 2 IMM 2
IX1 1 3 DIR 3 5 EXT 3 6 IX2 2 7 IX1 1 6
JMP JSR LDX JSR
DIR 3 3
IX 2 IX 5
3
BRCLR6
REL 2 3 REL 3
BTB 2 5
BCLR6
BSC 2 5
BMS
JSR LDX
EXT 3 4
JSR LDX
IX2 2 5
JSR LDX
IX1 1 4
3
Table 9-8 M68HC05 opcode map
BRSET7 CLR
DIR 1 INH 1 INH 2 IX1 1 IX 1 5
BTB 2 5
BSET7 CLRA
3
BSC 2 5
BIL CLRX
3
LDX TXA
2 INH 2
IX 3
3
CPU CORE AND INSTRUCTION SET
CLR
6
0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 CLR
5
BRCLR7
REL 2
BTB 2 5
BCLR7
BSC 2 5
BIH
WAIT
INH 2 INH 1
STX
DIR 3 4 DIR 3
STX
EXT 3 5 EXT 3
STX
IX2 2 6 IX2 2
STX
IX1 1 5 IX1 1
STX
IX 4 IX
3
BTB 2
BSC 2
Low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111
Abbreviations for address modes and registers
Legend F 1111 Mnemonic
1
Opcode in hexadecimal Opcode in binary SUB Not implemented Bytes Cycles Address mode
3 IX
BSC BTB DIR EXT INH IMM IX IX1 IX2 REL A X Indexed (no offset) Indexed, 1 byte (8-bit) offset Indexed, 2 byte (16-bit) offset Relative Accumulator Index register
Bit set/clear Bit test and branch Direct Extended Inherent Immediate
MC68HC05BD3
0 0000
TPG
9.3
Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) enable access to tables throughout memory. Short absolute (direct) and long absolute (extended) addressing are also included. One or two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory locations. The term `effective address' (EA) is used in describing the various addressing modes. The effective address is defined as the address from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate `contents of' the location or register referred to. For example, (PC) indicates the contents of the location pointed to by the PC (program counter). An arrow indicates `is replaced by' and a colon indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to the M68HC05 Applications Guide.
9.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator, as well as the control instruction, with no other arguments are included in this mode. These instructions are one byte long.
9
9.3.2
Immediate
In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g. a constant used to initialize a loop counter). EA = PC+1; PC PC+2
9.3.3
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1)
TPG
MC68HC05BD3
CPU CORE AND INSTRUCTION SET
MOTOROLA 9-11
9.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere in memory with a single three-byte instruction. When using the Motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the short form of the instruction. EA = (PC+1):(PC+2); PC PC+3 Address bus high (PC+1); Address bus low (PC+2)
9.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. EA = X; PC PC+1 Address bus high 0; Address bus low X
9.3.6
Indexed, 8-bit offset
9
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table. EA = X+(PC+1); PC PC+2 Address bus high K; Address bus low X+(PC+1) where K = the carry from the addition of X and (PC+1)
9.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. EA = X+[(PC+1):(PC+2)]; PC PC+3 Address bus high (PC+1)+K; Address bus low X+(PC+2) where K = the carry from the addition of X and (PC+2)
TPG
MOTOROLA 9-12
CPU CORE AND INSTRUCTION SET
MC68HC05BD3
9.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from -126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. EA = PC+2+(PC+1); PC EA if branch taken; otherwise EA = PC PC+2
9.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1)
9.3.10
Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branch is from -125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. EA1 = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) EA2 = PC+3+(PC+2); PC EA2 if branch taken; otherwise PC PC+3
9
TPG
MC68HC05BD3
CPU CORE AND INSTRUCTION SET
MOTOROLA 9-13
THIS PAGE LEFT BLANK INTENTIONALLY
9
TPG
MOTOROLA 9-14
CPU CORE AND INSTRUCTION SET
MC68HC05BD3
10
LOW POWER MODES
The MC68HC05BD3 has only one low-power operating mode-the Wait Mode. The WAIT instruction provides the only mode that reduces the power required for the MCU by stopping CPU internal clock. The STOP instruction is not implemented in its normal sense. The STOP instruction will be interpreted as the NOP instruction by the CPU if it is ever encountered. The flow of the WAIT mode is shown in Figure 10-1.
10.1
STOP Mode
Stop mode is not implemented on the MC68HC05BD3. The STOP instruction will be treated and executed as a NOP instruction. Therefore, the I-bit in the Condition Code register will not be cleared.
10.2
WAIT Mode
In the WAIT mode the internal processor clock is halted, suspending all processor and internal bus activities. Other Internal clocks remain active, permitting interrupts to be generated from the Multi-Function Timer, M-Bus Interface, and the Sync Signal Processor, or a reset to be generated from the COP watchdog timer. The timer may be used to generate a periodic exit from the WAIT mode. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code register, so that any hardware interrupt can wake up the MCU. All other registers, memory, and input/output lines remain in their previous states.
10
TPG
MC68HC05BD3
LOW POWER MODES
MOTOROLA 10-1
10.3
COP Watchdog Timer Considerations
The COP watchdog timer is always enabled in MC68HC05BD3. It will reset the MCU when it times out. For a system that must have intentional uses of the WAIT Mode, care must be taken to prevent such situations from happening during normal operations by arranging timely interrupts to reset the COP watchdog timer.
WAIT
External oscillator active and Internal Timer Clock Active
Stop internal processor clock, Clear I bit in CCR
External reset? N Internal COP reset?
Y
Y
10
N External H/W reset? N Internal interrupt? N 1. Fetch reset vector or 2. Service interrupt a. Stack b. Set I bit c. Vector to interrupt routine Y Restart internal processor clock Y
Figure 10-1 WAIT Flowchart
TPG
MOTOROLA 10-2
LOW POWER MODES
MC68HC05BD3
11
OPERATING MODES
The MC68HC05BD3/MC68HC05BD5/MC68HC705BD3 MCU has two modes of operation, the User Mode and the Self-Check/Bootstrap Mode. Figure 11-1 shows the flowchart of entry to these two modes, and Table 11-1 shows operating mode selection.
5V
RESET
9V
IRQ ? Y
N
USER MODE (NORMAL MODE)
PB5 = VDD ?
Y Note: Self-check mode is for MC68HC05BD3/BD5 Bootstrap mode is for MC68HC705BD3
SELF-CHECK/ BOOTSTRAP MODE
11
Figure 11-1 Flowchart of Mode Entering
TPG
MC68HC05BD3
OPERATING MODES
MOTOROLA 11-1
Table 11-1 Mode Selection
RESET
5V
IRQ VSS to VDD
9V
PB5 VSS to VDD VDD
MODE USER SELF-CHECK/ BOOTSTRAP
5V
+9V Rising Edge*
* Minimum hold time should be 2 clock cycles, after that it can be used as a normal IRQ function pin.
11.1
User Mode (Normal Operation)
The normal operating mode of the MC68HC05BD3/MC68HC05BD5/MC68HC705BD3 is the user mode. The user mode will be entered if the RESET line is brought low, and the IRQ pin is within its normal operational range (VSS to VDD), the rising edge of the RESET will cause the MCU to enter the user mode.
11.2
Self-Check Mode
11
The self-check mode is provided on the MC68HC05BD3 and MC68HC05BD5 for the user to check device functions with an on-chip self-check program masked at location $3F00 to $3FDF under minimum hardware support. The hardware is shown in Figure 11-3. Figure 11-2 is the criteria to enter self-check mode, where PB5's condition is latched within first two clock cycles after the rising edge of the reset. PB5 can then be used for other purposes. After entering the self-check mode, CPU branches to the self-check program and carries out the self-check. Self-check is a repetitive test, i.e. if all parts are checked to be good, the CPU will repeat the self-check again. Therefore, the LEDs attached to Port B will be flashing if the device is good; else the combination of LEDs' on-off pattern can show what part of the device is suspected to be bad. Table 11-2 lists the LEDs' on-off patterns and their corresponding indications.
+5V
PB5
+9V
IRQ
+5V
RESET
Figure 11-2 Self-Check Mode Timing
TPG
MOTOROLA 11-2
OPERATING MODES
MC68HC05BD3
+5V +9V 8 x 4K7 10K IRQ 10K 2N3904 10K PD0/SDA PD1/SCL PC0/PWM8 PC1/PWM9 PC2/PWM10 VSYNC PC3/PWM11 HSYNC PC4/PWM12 PC5/PWM13 XTAL PC6/PWM14/VTTL PC7/PWM15/HTTL EXTAL 8 x 100 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 +5V VDD VSS
4MHz +5V
MC68HC05BD3 10K RESET RESET 2.2 + +5V 20p 1N4148 20p
3 x 4K7 +5V 1K PB0 D1 1K PB1 D2 1K D3 PB2 PB3 PB4 PB5
11
0.1
+ 47
Figure 11-3 MC68HC05BD3 Self-Test Circuit
TPG
MC68HC05BD3
OPERATING MODES
MOTOROLA 11-3
Table 11-2 Self-Check Report
PB1 PB0 Flashing 1 1 0 1 0 1 1 0 0 0 1 1 1=LED off, 0=LED on PB3 REMARKS O.K. (self-check is on-going) Bad I/O BAD RAM BAD ROM BAD IRQ
11.3
Bootstrap Mode
The bootstrap mode is provided in the EPROM part (MC68HC705BD3) as a mean of self-programming its EPROM with minimal circuitry. It is entered on the rising edge of RESET if IRQ pin is at 1.8VDD and PB5 is at logic one. RESET must be held low for 4064 cycles after POR (power-on reset) or for a time tRL for any other reset. The user EPROM consists of 7.75K-bytes, from location $2000 to $3EFF. Refer to Section 15 for further details on MC68HC705BD3.
11
TPG
MOTOROLA 11-4
OPERATING MODES
MC68HC05BD3
12
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications for MC68HC05BD3.
12.1
Maximum Ratings
(Voltages referenced to VSS) RATINGS Supply Voltage Input Voltage IRQ Current Drain per pin excluding VDD and VSS Operating Temperature Storage Temperature Range
SYMBOL VDD Vin Vin ID TA Tstg
VALUE -0.3 to +7.0 VSS -0.3 to VDD +0.3 VSS -0.3 to 2xVDD +0.3 25 0 to 70 -65 to +150
UNIT V V V mA C C
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout)VDD. Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g. either VSS or VDD).
12.2
Thermal Characteristics
CHARACTERISTICS Thermal resistance - Plastic 40-pin DIP package - Plastic 42-pin SDIP package SYMBOL JA JA VALUE 60 60 UNIT C/W C/W
12
TPG
MC68HC05BD3
ELECTRICAL SPECIFICATIONS
MOTOROLA 12-1
12.3
DC Electrical Characteristics
Table 12-1 DC Electrical Characteristics for MC68HC05BD3
(VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) CHARACTERISTICS SYMBOL MINIMUM Output voltage ILOAD = -10A VOH VDD-0.1 ILOAD = +10A VOL - Output high voltage (ILOAD=-5mA) VOH VDD-0.8 PA0-PA7, PB0-PB1, PC6-PC7, PD0-PD1 Output low voltage (ILOAD=+5mA) PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VOL - PWM0-PWM7 Input high voltage PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VIH 0.7xVDD IRQ, RESET, EXTAL 2.0 VSYNC, HSYNC (TTL level) Input low voltage PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VIL VSS IRQ, RESET, EXTAL VSS VSYNC, HSYNC (TTL level) Supply current: Run IDD - Wait - I/O ports high-Z leakage current PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, IIL - PWM0-PWM7 Input current IIN - IRQ, RESET, EXTAL, VSYNC, HSYNC Capacitance COUT - ports (as input or output), RESET, IRQ, CIN - EXTAL, XTAL, HSYNC, VSYNC Notes: (1) All values shown reflect average measurements. (2) Typical values at midpoint of voltage range, 25C only. (3) Wait IDD: only timer system and SSP is active.
TYPICAL - - - -
MAXIMUM - 0.1 - 0.4
UNIT V V V V
- - - -
VDD VDD
V
0.2xVDD 0.8 20 8 10 1 12 8
V
4.5 0.73 - - - -
mA mA A A pF pF
12
(4) Run (operating) IDD, Wait IDD: measured using external square wave clock source to EXTAL (fOSC =4.2MHz), all inputs 0.2 Vdc from rail; no dc loads, less than 50pF on all outputs, CL =20pF on EXTAL. (5) Wait IDD: all ports configured as inputs, VIL =0.2 Vdc, VIH =VDD - 0.2 Vdc. (6) Wait IDD is affected linearly by the EXTAL capacitance.
TPG
MOTOROLA 12-2
ELECTRICAL SPECIFICATIONS
MC68HC05BD3
12.4
Control Timing
Table 12-2 Control Timing
(VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) CHARACTERISTICS SYMBOL MINIMUM MAXIMUM UNIT Frequency of operation - 4.2 MHz Crystal option fOSC dc 4.2 MHz External clock option Internal operating frequency (fOSC/2) Crystal fOP - 2.1 MHz External clock fOP dc 2.1 MHz 480 - ns Processor cycle time tCYC Crystal oscillator start-up time tOXOV - 100 ms External RESET pulse width tRL 1.5 - tCYC Watchdog RESET output pulse width tDOGL 1.5 - tCYC Watchdog time-out tDOG 114688 917504 tCYC Interrupt pulse width (edge-triggered) tILIH 125 - ns Interrupt pulse period tILIL -(1) - tCYC EXTAL pulse width tOH, tOL 100 - tCYC Notes: (1) The minimum period tILIL should not be less than the number of cycles it takes to execute the interrupt service routine plus 21 tCYC.
12
TPG
MC68HC05BD3
ELECTRICAL SPECIFICATIONS
MOTOROLA 12-3
12.5
M-Bus Timing
Table 12-3 M-Bus Interface Input Signal Timing
(VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) PARAMETER SYMBOL MINIMUM START condition hold time tHD.STA 2 Clock low period tLOW 4.7 Clock high period tHIGH 4 Data set-up time tSU.DAT 250 Data hold time tHD.DAT 0 START condition set-up time 2 tSU.STA (for repeated START condition only) STOP condition set-up time tSU.STO 2
MAXIMUM - - - - - - -
UNIT tCYC tCYC tCYC ns tCYC tCYC tCYC
Table 12-4 M-Bus Interface Output Signal Timing
(VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) PARAMETER SYMBOL MINIMUM START condition hold time tHD.STA 8 Clock low period tLOW 11 Clock high period tHIGH 11 SDA/SCL rise time (see note 1) tR - SDA/SCL fall time (see note 1) tF - Data set-up time tSU.DAT tLOW - tCYC Data hold time tHD.DAT 1 START condition set-up time tSU.STA 10 (for repeated START condition only) STOP condition set-up time tSU.STO 10 Note: 1. With 200pF loading on the SDA/SCL pins
MAXIMUM - - - 1 300 - - - -
UNIT tCYC tCYC tCYC s ns ns tCYC tCYC tCYC
12
SDA tF SCL tR
tHD.STA
tLOW
tHIGH
tSU.DAT
tHD.DAT
tSU.STA
tSU.STO
Figure 12-1 M-Bus Timing
TPG
MOTOROLA 12-4
ELECTRICAL SPECIFICATIONS
MC68HC05BD3
12.6
Sync Signal Processor Timing
Table 12-5 Sync Signal Processor Timing
(VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) PARAMETER SYMBOL VSYNC input sync pulse tVI.SP HSYNC input sync pulse tHI.SP (except for composite sync input) VTTL output sync pulse width for separate sync input tVO.SP VTTL output sync pulse width for composite sync input tVO.CO HTTL output sync pulse width tHO Free-running VTTL output sync pulse (SOUT clear) tFVO.SP Free-running VTTL output period (SOUT clear) tFVO Free-running HTTL output sync pulse (SOUT clear) tFHO.SP Free-running HTTL output period (SOUT clear) tFHO Inserted HTTL sync pulse (INSRT cleared) tIHI.SP Inserted HTTL period error (INSRT cleared) tIHI.ER VSYNC to VTTL delay (8pF loading) tVDD HSYNC to HTTL delay (8pF loading) tHHD HSYNC to VTTL delay (composite sync) tHVD
MINIMUM 1 1
MAXIMUM
UNIT tCYC tCYC
same as input input + 9.5s input + 10s same as input 128 31488 4 41/32 4 - 1 30 40 30 40 30 40
tCYC tCYC tCYC tCYC tCYC tCYC ns ns ns
12
TPG
MC68HC05BD3
ELECTRICAL SPECIFICATIONS
MOTOROLA 12-5
THIS PAGE LEFT BLANK INTENTIONALLY
12
TPG
MOTOROLA 12-6
ELECTRICAL SPECIFICATIONS
MC68HC05BD3
13
MECHANICAL SPECIFICATIONS
This section provides the mechanical dimension for the 42-pin SDIP and 40-pin DIP packages for the MC68HC05BD3.
13.1
42
42-Pin SDIP Package (Case 858-01)
-A22 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
-B1 21
L C H
-TSEATING PLANE
F D 42 PL 0.25 (0.010)
M
G TA
S
N K J 42 PL 0.25 (0.010)
M
M TB
S
DIM A B C D F G H J K L M N
INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.032 0.046 0.070 BSC 0.300 BSC 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 5.08 3.94 0.56 0.36 1.17 0.81 1.778 BSC 7.62 BSC 0.38 0.20 3.43 2.92 15.24 BSC 15 0 1.02 0.51
13.2
40
40-Pin DIP Package (Case 711-03)
21 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
B
1 20
A N
C
L
13
J H G F D K
SEATING PLANE
M
TPG
MC68HC05BD3
MECHANICAL SPECIFICATIONS
MOTOROLA 13-1
THIS PAGE LEFT BLANK INTENTIONALLY
13
TPG
MOTOROLA 13-2
MECHANICAL SPECIFICATIONS
MC68HC05BD3
14
MC68HC705BD3
The MC68HC705BD3 is functionally equivalent to MC68HC05BD3, but with increased RAM size to 256 bytes and the user ROM is replaced by an 7.75K-bytes user EPROM (located from $2000 to $3EFF). The entire MC68HC05BD3 data sheet applies to the MC68HC705BD3, with exceptions outlined in the section.
14.1
* * *
Features
Functionally equivalent to MC68HC05BD3 256 bytes on-chip RAM 7.75K-bytes user EPROM
14.2
Memory Map
Figure 14-1 shows the memory map for the MC68HC705BD3.
14.3
EPROM Programming
The following programming boards are available from Motorola for programming the on-chip EPROM in the MC68HC705BD3.
Table 14-1 MC68HC705BD3 Programming Boards
Platform board For programming a single device at a time: For programming up to 10 devices at a time: Adapter M68UPA05BD3P40 for 40-pin PDIP M68UPA05BD3B42 for 42-pin SDIP
M68HC705UPGMR M68HC705UGANG
+
14
TPG
MC68HC05BD3
MC68HC705BD3
MOTOROLA 14-1
MC68HC705BD3 $0000 $002F $0030 Unused $007F $0080 $00C0 $00FF
Stack 64 Bytes
I/O 48 Bytes
User RAM 256 Bytes $017F $0180
Unused
$1DFF $1E00 Bootstrap ROM 480 Bytes $1FDF $1FE0 $1FFF $2000
Unused
User EPROM 7936 Bytes
$3EFF $3F00 Unused $3FDF $3FE0 $3FEF $3FF0 $3FFF
Bootstrap Vectors 16 Bytes User Vectors 16 Bytes
Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register MFT Control and Status Register MFT Timer Counter Register Configuration Register 1 Configuration Register 2 SSP Control and Status Register Vertical Frequency High Register Vertical Frequency Low Register Line Frequency High Register Line Frequency Low Register Sync Signal Control Register Unused Unused Unused Unused Unused MBUS Address Register MBUS Frequency Divider Register MBUS Control Register MBUS Status Register MBUS Data Register Unused Programming Control Register HSYNC Period Width Register Reserved PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 PWM14 PWM15 $3FF0 $3FF2 $3FF4 $3FF6 $3FF8 $3FFA $3FFC $3FFE Reserved Reserved MFT MBUS SSP IRQ SWI RESET
$00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F
14
MOTOROLA 14-2
TPG
MC68HC705BD3
MC68HC05BD3
14.3.1
Programming Control Register (PCR)
The EPROM Programming Control register controls the actual programming of the EPROM in the MC68HC705BD3.
Address $001D bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 ELAT bit 0 PGM State on reset ---- --00
ELAT - EPROM Latch Control 1 (set) - EPROM address and data bus configured for programming (writes to EPROM cause address data to be latched). EPROM is in programming mode and cannot be read if ELAT is 1. This bit is not able be set when no VPP voltage is applied to the VPP pin. EPROM address and data bus configured for normal reads.
0 (clear) -
PGM - EPROM Program Command 1 (set) - Programming power switched on to EPROM array. If ELAT1 then PGM=0. Programming power switched off to EPROM array.
0 (clear) -
14.3.2
EPROM Programming Sequence
Programming the EPROM of the MC68HC705BD3 is as follows: 1) Set the ELAT bit. 2) Write the data to be programmed to the address to be programmed. 3) Set the PGM bit. 4) Delay for the appropriate amount of time. 5) Clear the PGM and the ELAT bits. The last action may be carried out in a single CPU write operation. It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but should be equal to VDD during normal operation. Example shows address $2000 is programmed with $00. CLR LDX BSET LDA STA PCR #$00 1,PCR #$00 $2000,X ;reset PCR ;load index register with 00 ;set ELAT bit ;load data=00 in to A ;latch data and address
14
TPG
MC68HC05BD3
MC68HC705BD3
MOTOROLA 14-3
BSET JSR CLR
0,PCR DELAY PCR
;program ;call delay subroutine ;reset PCR
14.4
DC Electrical Characteristics
Table 14-2 DC Electrical Characteristics for MC68HC705BD3
(VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) CHARACTERISTICS SYMBOL MINIMUM Output voltage VOH VDD-0.1 ILOAD = -10A ILOAD = +10A VOL - Output high voltage (ILOAD=-5mA) VOH VDD-0.8 PA0-PA7, PB0-PB1, PC6-PC7, PD0-PD1 Output low voltage (ILOAD=+5mA) PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VOL - PWM0-PWM7 Input high voltage PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VIH 0.7xVDD IRQ, RESET, EXTAL 2.0 VSYNC, HSYNC (TTL level) Input low voltage PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VIL VSS IRQ, RESET, EXTAL VSS VSYNC, HSYNC (TTL level) Supply current: Run IDD - Wait - I/O ports high-Z leakage current PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, IIL - PWM0-PWM7 Input current IIN - IRQ, RESET, EXTAL, VSYNC, HSYNC Capacitance COUT - ports (as input or output), RESET, IRQ, CIN - EXTAL, XTAL, HSYNC, VSYNC Notes: (1) All values shown reflect average measurements. (2) Typical values at midpoint of voltage range, 25C only. (3) Wait IDD: only timer system and SSP is active.
TYPICAL - - - -
MAXIMUM - 0.1 - 0.4
UNIT V V V V
- - - -
VDD VDD
V
0.2xVDD 0.8 20 8 10 1 12 8
V
6 2 - - - -
mA mA A A pF pF
14
(4) Run (operating) IDD, Wait IDD: measured using external square wave clock source to EXTAL (fOSC =4.2MHz), all inputs 0.2 Vdc from rail; no dc loads, less than 50pF on all outputs, CL =20pF on EXTAL. (5) Wait IDD: all ports configured as inputs, VIL =0.2 Vdc, VIH =VDD - 0.2 Vdc. (6) Wait IDD is affected linearly by the EXTAL capacitance.
TPG
MOTOROLA 14-4
MC68HC705BD3
MC68HC05BD3
15
MC68HC05BD5
The MC68HC05BD5 is functionally equivalent to MC68HC05BD3, but with increased RAM size of 256 bytes and ROM size of 7.75K-bytes. The entire MC68HC05BD3 data sheet applies to the MC68HC05BD5, with exceptions outlined in the section.
15.1
* * *
Features
Functionally equivalent to MC68HC05BD3 256 bytes on-chip RAM 7.75K-bytes user ROM
15.2
Memory Map
Figure 15-1 shows the memory map for the MC68HC05BD5.
TPG
MC68HC05BD3
MC68HC05BD5
MOTOROLA 15-1
15
MC68HC05BD5 $0000 $002F $0030 I/O 48 Bytes Port A Data Register Port B Data Register Port C Data Register Port D Data Register Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register Port D Data Direction Register MFT Control and Status Register MFT Timer Counter Register Configuration Register 1 Configuration Register 2 SSP Control and Status Register Vertical Frequency High Register Vertical Frequency Low Register Line Frequency High Register Line Frequency Low Register Sync Signal Control Register Unused Unused Unused Unused Unused MBUS Address Register MBUS Frequency Divider Register MBUS Control Register MBUS Status Register MBUS Data Register Unused Reserved HSYNC Period Width Register Reserved PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 PWM14 PWM15 $3FF0 $3FF2 $3FF4 $3FF6 $3FF8 $3FFA $3FFC $3FFE Reserved Reserved MFT MBUS SSP IRQ SWI RESET $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F
Unused $007F $0080 $00C0 $00FF
Stack 64 Bytes
User RAM 256 Bytes $017F $0180
Unused
$1FFF $2000
User ROM 7936 Bytes
$3EFF $3F00
Self-Check Program 224 Bytes Self-Check Vectors 16 Bytes User Vectors 16 Bytes
$3FDF $3FE0 $3FEF $3FF0 $3FFF
15
TPG
MOTOROLA 15-2
MC68HC05BD5
MC68HC05BD3
15.3
DC Electrical Characteristics
Table 15-1 DC Electrical Characteristics for MC68HC05BD5
(VDD =5.0Vdc 10%, VSS =0Vdc, temperature range=0 to 70C) CHARACTERISTICS SYMBOL MINIMUM Output voltage ILOAD = -10A VOH VDD-0.1 ILOAD = +10A VOL - Output high voltage (ILOAD=-5mA) VOH VDD-0.8 PA0-PA7, PB0-PB1, PC6-PC7, PD0-PD1 Output low voltage (ILOAD=+5mA) PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VOL - PWM0-PWM7 Input high voltage PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VIH 0.7xVDD IRQ, RESET, EXTAL 2.0 VSYNC, HSYNC (TTL level) Input low voltage PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, VIL VSS IRQ, RESET, EXTAL VSS VSYNC, HSYNC (TTL level) Supply current: Run IDD - Wait - I/O ports high-Z leakage current PA0-PA7, PB0-PB5, PC0-PC7, PD0-PD1, IIL - PWM0-PWM7 Input current IIN - IRQ, RESET, EXTAL, VSYNC, HSYNC Capacitance COUT - ports (as input or output), RESET, IRQ, CIN - EXTAL, XTAL, HSYNC, VSYNC Notes: (1) All values shown reflect average measurements. (2) Typical values at midpoint of voltage range, 25C only. (3) Wait IDD: only timer system and SSP is active. (4) Run (operating) IDD, Wait IDD: measured using external square wave clock source to EXTAL (fOSC =4.2MHz), all inputs 0.2 Vdc from rail; no dc loads, less than 50pF on all outputs, CL =20pF on EXTAL. (5) Wait IDD: all ports configured as inputs, VIL =0.2 Vdc, VIH =VDD - 0.2 Vdc. (6) Wait IDD is affected linearly by the EXTAL capacitance.
TYPICAL - - - -
MAXIMUM - 0.1 - 0.4
UNIT V V V V
- - - -
VDD VDD
V
0.2xVDD 0.8 20 8 10 1 12 8
V
7 1.3 - - - -
mA mA A A pF pF
TPG
MC68HC05BD3
MC68HC05BD5
MOTOROLA 15-3
15
THIS PAGE LEFT BLANK INTENTIONALLY
15
TPG
MOTOROLA 15-4
MC68HC05BD5
MC68HC05BD3
GENERAL DESCRIPTION PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3
TPG MC68HC05BD5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
GENERAL DESCRIPTION PIN DESCRIPTION AND I/O PORTS MEMORY AND REGISTERS RESETS AND INTERRUPTS MULTI-FUNCTION TIMER PULSE WIDTH MODULATION M-BUS SERIAL INTERFACE SYNC SIGNAL PROCESSOR CPU CORE AND INSTRUCTION SET LOW POWER MODES OPERATING MODES ELECTRICAL SPECIFICATIONS MECHANICAL SPECIFICATIONS MC68HC705BD3 MC68HC05BD5
TPG
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 2 3 4 5 6 7 8 9 10 11 12 13 14
How to reach us: MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
15 !MOTOROLA
MC68HC05BD3D/H

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